Variable time slot assignment of virtual processors

Claim 2

A multiprogram multiprocessor digital data processing system which receives and transmits digital information and has the capability of storing the digital information and performing data processing operations of the digital information, the combination comprising: a. a peripheral processing unit having a plurality of virtual processors each processor including storage means for storing digital information and operation instructions; b. an arithmetic unit in said peripheral processor unit for performing arithmetic and logic manipulative operations on the digital information including means for selectively receiving digital information from and transmitting digital information to time-share the arithmetic unit; and c. means for connecting selected ones of said virtual processors successively to said arithmetic unit for the performance of the operation instructions of said virtual processors on the digital information for time intervals dependent upon changeable stored program dependent weighting functions.

Claim 3

A multiprogrammed multiprocessor digital computer having components including memory, the combination which comprises: a. a peripheral processing unit having a time-shared high-speed arithmetic unit for processing data; b. a plurality of virtual processors having data channels leading to said arithmetic unit; c. a common bus for communication between said memory, said arithmetic unIt, and said virtual processors; and d. means including addressable code storage means in said peripheral processing unit for allocating to said virtual processors the time said arithmetic unit is available to each said processor.

Claim 4

A multiprogrammed multiprocessor digital computer having components including memory, the combination which comprises: a. a peripheral processing unit having a time-shared high-speed arithmetic unit for processing data; b. a plurality of virtual processors having data channels leading to said arithmetic unit; c. a common bus for communication between said memory, said arithmetic unIt, and said virtual processors; and d. means including addressable code storage means in said peripheral processing unit for allocating to said virtual processors the time said arithmetic unit is available to each said processor.

Claim 5

The combination set forth in claim 2 wherein said peripheral processing unit includes a file of single word buffer registers, one for each virtual processor for communication between said memory and said virtual processors.

Claim 6

A multiprogrammed multiprocessor digital data processing system which comprises: a. a central processing unit; b. a peripheral processing unit for servicing said central processing unit at least in part through operation of an arithmetic unit therein; c. a plurality of virtual processors in said peripheral processor having connection means operable at clock rate to be connected one at a time to time-share said arithmetic unit; and d. means including a sequencer for varying the selection of the said connections means for allocation to one or more of said virtual processors more of the time of said arithmetic unit than other virtual processors.

Claim 7

A multiprogrammed multiprocessor digital data processing system which comprises: a. a central processing unit; b. a peripheral processing unit for servicing said central processing unit at least in part through operation of an arithmetic unit therein; c. a plurality of virtual processors in said peripheral processor having connection means operable at clock rate to be connected one at a time to time-share said arithmetic unit; and d. means including a sequencer for varying the selection of the said connections means for allocation to one or more of said virtual processors more of the time of said arithmetic unit than other virtual processors.

Claim 8

The combination set forth in claim 4 wherein a common addressable communication register accessible to all of said virtual processors has register segments connected to said sequencer to control said allocation in dependence upon codes in said segments.

Claim 9

The combination set forth in claim 4 wherein said sequencer includes a clock, logic means and a decoder to permit access by said virtual processors to said arithmetic unit as frequently as once each cycle of said clock.

Claim 10

A multiprogrammed multiprocessor digital wherein digital information is operated upon according to programmed data processing steps, the combination comprising: a. a central processing unit having memory means for storing a plurality of user program instructions and digital information and including means for selectively executing sequential instructions of said user program; b. a peripheral processing unit having a plurality of virtual processors and an arithmetic unit accessed by said virtual processors on a time-shared basis for scheduling the sequence of execution of said user program instructions according to programmed criteria and including look-ahead means for providing an indication of the user program instruction to be next executed by said peripheral processor system as said central processing unit is responding to the immediate instruction; and c. means connected between said arithmetic unit and said virtual processors for automatically controlling the sequential selection on a time-shared basis of user program instructions and data to be placed in operation in said central processing unit.

Claim 11

A multiprogrammed multiprocessor digital wherein digital information is operated upon according to programmed data processing steps, the combination comprising: a. a central processing unit having memory means for storing a plurality of user program instructions and digital information and including means for selectively executing sequential instructions of said user program; b. a peripheral processing unit having a plurality of virtual processors and an arithmetic unit accessed by said virtual processors on a time-shared basis for scheduling the sequence of execution of said user program instructions according to programmed criteria and including look-ahead means for providing an indication of the user program instruction to be next executed by said peripheral processor system as said central processing unit is responding to the immediate instruction; and c. means connected between said arithmetic unit and said virtual processors for automatically controlling the sequential selection on a time-shared basis of user program instructions and data to be placed in operation in said central processing unit.

Claim 12

The combination set forth in claim 7 wherein there is an addressable register file accessible to all of said virtual processors for storage of said indication.