Multiple microprocessor intercommunication arrangement

Claim 1

A multiple microprocessor interconnection arrangement comprising at least a first and a second microprocessor unit, each microprocessor unit being adapted to concurrently perform a different function from that being performed by the other microprocessor units; an interconnection channel comprising a memory unit connected to each of said at least first and second microprocessor units and a multiplexer disposed between each of said first and second microprocessor units and said memory unit, said memory unit including a plurality of memory locations accessible to each of said at least first and second microprocessor units; and timing means connected to each of said at least first and second microprocessor units and said multiplexer of the interconnection channel, said timing means being capable of generating timing signals which both produce a normal operational timing cycle for each microprocessor unit which is offset by a predetermined amount from the timing cycle of each of the other microprocessor units and cause the multiplexer to sequentially connect each of said at least first and second microprocessor units to said memory unit for accessing and performing a read or write function in a desired memory location in said memory unit during a predetermined corresponding portion of each microprocessor unit's timing cycle which does not overlap the corresponding portion of another microprocessor unit's offset timing cycle.

Claim 9

A method of permitting each of a plurality of n microprocessor units to access a memory unit common to all of the plurality of n microprocessor units without the necessity for contention resolving means, the method comprising the steps of: (a) concurrently generating separate timing signals which form the normal operational timing cycle for each microprocessor unit of the plurality of n microprocessor units, the operational timing cycle for each microprocessor unit being at a different 1/n phase of the normal operational timing cycle at any instant of time; and (b) in response to the timing signals generated in step (a), permitting each of the plurality of n microprocessor units to access the common memory unit only during the 1/n phase of its normal operational timing cycle which ends with the latching by either one of the microprocessor unit and the common memory unit of data being transmitted therebetween.

Claim 10

A method of permitting each of a plurality of n microprocessor units to access a memory unit common to all of the plurality of n microprocessor units without the necessity for contention resolving means, the method comprising the steps of: (a) concurrently generating separate timing signals which form the normal operational timing cycle for each microprocessor unit of the plurality of n microprocessor units, the operational timing cycle for each microprocessor unit being at a different 1/n phase of the normal operational timing cycle at any instant of time; and (b) in response to the timing signals generated in step (a), permitting each of the plurality of n microprocessor units to access the common memory unit only during the 1/n phase of its normal operational timing cycle which ends with the latching by either one of the microprocessor unit and the common memory unit of data being transmitted therebetween.

Claim 11

A method of permitting each of a plurality of n microprocessor units to access a memory unit common to all microprocessor units without the necessity for contention resolving means where each microprocessor unit comprises a separate associated memory wherein is stored its operational program, the method comprising the steps of: (a) concurrently generating timing signals which form the normal operational timing cycle for each microprocessor unit of the plurality of n microprocessor units, the operational timing cycle for each microprocessor unit of the pluality of n microprocessor units being at a different 1/n phase of the normal operational timing cycle at any instant of time; (b) decoding the memory address generated by each microprocessor unit of the plurality of n microprocessor units for determining which memory of either one of the separate associated memory and the common memory unit is desired to be accessed by each of the microprocessor units; (c) in response to step (b) transmitting an enable signal to the memory to be accessed by each of the microprocessor units; and (d) in response to the timing signals of step (a) and the enable signals of step (c), permitting each of the plurality of n microprocessor units to access either one of (1) its separate associated memory during the normal period of its operational timing cycle designated for such access, and (2) the common memory unit only during the 1/n phase of its normal operational timing cycle which ends with the latching by either one of the microprocessor unit and the common memory unit of data being transmitted therebetween.

Claim 12

A method of permitting each of a plurality of n microprocessor units to access a memory unit common to all microprocessor units without the necessity for contention resolving means where each microprocessor unit comprises a separate associated memory wherein is stored its operational program, the method comprising the steps of: (a) concurrently generating timing signals which form the normal operational timing cycle for each microprocessor unit of the plurality of n microprocessor units, the operational timing cycle for each microprocessor unit of the pluality of n microprocessor units being at a different 1/n phase of the normal operational timing cycle at any instant of time; (b) decoding the memory address generated by each microprocessor unit of the plurality of n microprocessor units for determining which memory of either one of the separate associated memory and the common memory unit is desired to be accessed by each of the microprocessor units; (c) in response to step (b) transmitting an enable signal to the memory to be accessed by each of the microprocessor units; and (d) in response to the timing signals of step (a) and the enable signals of step (c), permitting each of the plurality of n microprocessor units to access either one of (1) its separate associated memory during the normal period of its operational timing cycle designated for such access, and (2) the common memory unit only during the 1/n phase of its normal operational timing cycle which ends with the latching by either one of the microprocessor unit and the common memory unit of data being transmitted therebetween.