Data processing system

Claim 2

In a data processing system having at least one data accessing control unit, a memory unit comprising a plurality of memory modules, timing means associated with each memory module for initiating the operating time cycles thereof, said memory modules being capable of synchronous or non-synchronous operation and of sequential access by said at least one data accessing control unit and of sequential transfer of data with respect thereto; a first memory module including means for permitting said first memory module to be accessed by a data accessing control unit after a second of said memory modules has been accessed by a data accessing control unit and before a transfer of data is completed with respect to said second memory module; means for sensing when the transfer of data with respect to said second memory module is completed; and means for permitting a transfer of data with respect to said first memory module when the transfer of data with respect to said second memory module has been completed.

Claim 3

In a data processing system having at least one data accessing control unit, a memory unit comprising a plurality of memory modules interconnected by module interconnecting means, said modules being capable of synchronous or non-synchronous operation; means for sequentially transferring addresses from said at least one data accessing control unit to the memory modules of said memory unit; means for sequentially transferring data between said at least one data accessing control unit and the memory modules of said memory unit; each module including timing means for initiating the operating time cycle of said each memory module in response to an address transferred thereto from a data accessing control unit; memory control means including means for generating a data transfer status signal to indicate the data transfer status of said each memory module, the data transfer status signals of each memory module being made available by said module interconnecting means to all of said memory modules; and means responsive to a said timing means and to data transfer status signal from another of said memory modules which had been previously started for preventing a transfer of data with respect to said each memory module before data has been completely transferred with respect to said another previously started memory module and including means for permitting a transfer of data with respect to said each memory module when the transfer of data with respect to said another previously started memory module has been completed; said timing means further including means permitting the operating time cycle of said each memory module to be started before the transfer of data between said another previously started memory module has been completed.

Claim 4

In a data processing system having at least one data accessing control unit, a memory unit comprising a plurality of memory modules interconnected by module interconnecting means, said modules being capable of synchronous or non-synchronous operation; means for sequentially transferring addresses from said at least one data accessing control unit to the memory modules of said memory unit; means for sequentially transferring data between said at least one data accessing control unit and the memory modules of said memory unit; each module including timing means for initiating the operating time cycle of said each memory module in response to an address transferred thereto from a data accessing control unit; memory control means including means for generating a data transfer status signal to indicate the data transfer status of said each memory module, the data transfer status signals of each memory module being made available by said module interconnecting means to all of said memory modules; and means responsive to a said timing means and to data transfer status signal from another of said memory modules which had been previously started for preventing a transfer of data with respect to said each memory module before data has been completely transferred with respect to said another previously started memory module and including means for permitting a transfer of data with respect to said each memory module when the transfer of data with respect to said another previously started memory module has been completed; said timing means further including means permitting the operating time cycle of said each memory module to be started before the transfer of data between said another previously started memory module has been completed.

Claim 5

A data processing system in accordance with claim 2 wherein said address transferring means is a single address bus; and said data transferring means is a single data bus.

Claim 6

A data processing system in accordance with claim 3 wherein said timing means of said each memory module comprises address select means responsive to addresses on said address bus for identifying selected addresses for said each memory module; and memory instruction means responsive to said selected addresses for providing a signal for starting the operation of said each memory module.

Claim 7

A data processing system in accordance with claim 4 wherein each memory module includes memory buffer means for temporarily storing data for transfer between said each memory module and said data bus; memory status means for providing a plurality of memory status signals for controlling the operation of said each memory module, said memory status signals including signals indicating whether said memory module has a data transfer pending, whether said memory module is awaiting access to said data bus for a data transfer operation, and whether data from said memory module is to be stored in said memory buffer means.

Claim 8

A data processing system in accordance with claim 1 wherein the storage of data in said memory modules is arranged in an interleaved manner such that data which is expected to be referenced sequentially during the operation of said data processing means is sequentially stored in different memory modules.

Claim 9

A data processing system in accordance with claim 6 wherein said memory system comprises N memory modules, said data being stored in an N-way interleaving manner such that each sequential group of N sequential words is stored sequentially in said N memory modules.

Claim 10

A data processing system in accordance with claim 6 wherein said memory system comprises N memory modules, said data being stored in an N/2-way interleaving manner such that each sequential group of N/2 sequential words in a first plurality of groups is stored sequentially in a first group of N/2 of said memory modules and each sequential group of N/2 sequential words in a second plurality of groups is stored sequentially in a second group of N/2 of said memory modules.

Claim 11

A data processing system in accordance with claim 6 wherein said memory system comprises N memory modules, said data being stored in an N/4-way interleaving manner such that each sequential group of N/4 sequential words in a first plurality of groups is stored sequentially in a first group of N/4 of said memory modules, each sequential group of N/4 sequential words in a second plurality of groups is stored sequentially in a second group of N/4 of said memory modules, each sequential group of N/4 sequential words in a third plurality of groups is stored sequentially in a third group of N/4 of said memory modules, and each sequential group of N/4 sequential words in a fourth plurality of groups is stored sequentially in a fourth group of N/4 of said memory modules.

Claim 12

A data processing system in accordance with claim 7 wherein N is 8.

Claim 13

A data processing system in accordance with claim 8 wherein N is 8.

Claim 14

A data processing system in accordance with claim 9 wherein N is 8.