Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits

Claim 2

In a plurality of JTAG register chains having a Data Register and Instruction Register for holding status information on a plurality of logic elements wherein said register chains are set in an idle or an operative Run state, said logic elements having JTAG register chains for reading the condition of said logic elements, a system for selectively reading out the present state of any logic element in any one of said JTAG registers, said present state including a digital code which reflects the current JTAG state condition for a Data Register or Instruction Register, comprising: (a) means for setting said JTAG register chains into the operative Run state; (b) tracking means for reading out the presently existing said present state of any one of said logic element's JTAG register chain including: (b1) a dedicated state machine tracker for each one of said JTAG register chains which provides a coded output which indicates the specific JTAG present state occurring in that JTAG register chain; (c) means for shifting the said presently known readout present state in order to provide a readout of a newly selected JTAG register state.

Claim 3

The system of claim 1 wherein said tracking means for readout of a selected JTAG register state can be read out for display in one clock period.

Claim 4

The system of claim 1 which includes: (a) maintenance processor means for shifting test data input, clock signals and test mode select signals into each of said JTAG register chains; (b) test data output lines for conveying the state conditions of each said JTAG register chain to said maintenance processor.

Claim 5

The system of claim 3 wherein said maintenance processor means includes: means for diagnosing the operation of said logic elements by readout of the status of each register in each said JTAG register chain.

Claim 6

In an integrated circuit chip having multiple operative logic elements connected to multiple JTAG boundary scan registers which hold a digitally encoded state condition for each of said logic elements, a system for tracking and reading out the said digitally encoded state of any selected logic element comprising: (a) means for feeding test data into said multiple operative logic elements; (b) means for reading out said test data from said multiple operative logic elements; (c) a plurality for multiple JTAG registers each forming a JTAG register chain with each register holding digitally encoded state information reflective of one of said logic elements; (d) a plurality of JTAG state machine tracker means for sensing the digitally encoded state of each JTAG register chain and for enabling rapid readout of any selected present state condition in any of said JTAG registers.

Claim 7

In an integrated circuit chip having multiple operative logic elements connected to multiple JTAG boundary scan registers which hold a digitally encoded state condition for each of said logic elements, a system for tracking and reading out the said digitally encoded state of any selected logic element comprising: (a) means for feeding test data into said multiple operative logic elements; (b) means for reading out said test data from said multiple operative logic elements; (c) a plurality for multiple JTAG registers each forming a JTAG register chain with each register holding digitally encoded state information reflective of one of said logic elements; (d) a plurality of JTAG state machine tracker means for sensing the digitally encoded state of each JTAG register chain and for enabling rapid readout of any selected present state condition in any of said JTAG registers.

Claim 8

In a digital network having multiple integrated circuits each of which has a dedicated JTAG register chain for testing and diagnosing said integrated circuits wherein each said JTAG register chain operates through 14 states such that 7 states are sequenced for a data register and 7 states are sequenced for an instruction register using the standard 7-step sequence provided by the JTAG IEEE Standard 1149.1, a system for sensing the present state condition of each JTAG register chain comprising: (a) means for using a digital bit code to establish each state of said 7 data register sequences and 7 instruction register sequences plus codes for an Idle state and Run Test state; (b) means for setting each of said JTAG registers into said Run Test state; (c) means for stepping said Data Register and said Instruction Register through said sequence of 7 states; (d) JTAG tracker means including: (d1) a dedicated JTAG tracker for monitoring each one of said dedicated JTAG register chains; (d2) readout means for reading out the said digital bit code indicating the present state of a selected one of said dedicated JTAG register chains; (e) means for shifting the state of any one of said JTAG register chains from its presently known state to a desired subsequent state.

Claim 9

In a digital network having multiple integrated circuits each of which has a dedicated JTAG register chain for testing and diagnosing said integrated circuits wherein each said JTAG register chain operates through 14 states such that 7 states are sequenced for a data register and 7 states are sequenced for an instruction register using the standard 7-step sequence provided by the JTAG IEEE Standard 1149.1, a system for sensing the present state condition of each JTAG register chain comprising: (a) means for using a digital bit code to establish each state of said 7 data register sequences and 7 instruction register sequences plus codes for an Idle state and Run Test state; (b) means for setting each of said JTAG registers into said Run Test state; (c) means for stepping said Data Register and said Instruction Register through said sequence of 7 states; (d) JTAG tracker means including: (d1) a dedicated JTAG tracker for monitoring each one of said dedicated JTAG register chains; (d2) readout means for reading out the said digital bit code indicating the present state of a selected one of said dedicated JTAG register chains; (e) means for shifting the state of any one of said JTAG register chains from its presently known state to a desired subsequent state.