Boundary-scan test method and apparatus for diagnosing faults in a device under test

Claim 2

A boundary-scan tester for diagnosing a fault in a device under test (DUT), the DUT having boundary-scan cells coupled to respective input and output terminals thereof, comprising: (a) driver/receiver means for driving input terminals of the DUT with a parallel input vector and receiving a corresponding parallel output vector from output terminals of the DUT; (b) comparing means, coupled to said driver/receiver means, for comparing said output vector with an expected output vector and providing a failure signal indicative of the result thereof and defining a fault; (c) first control means, coupled to said driver/receiver means and said comparing means, for receiving said failure signal from said comparing means and in response thereto transmitting control signals to the DUT via said driver/receiver means, said control signals causing data captured by boundary-scan cells associated with the respective input and output terminals of the DUT to be serially shifted out to said driver/receiver means; and (d) storage means, coupled to said driver/receiver means, for storing said input and output vectors and the data shifted out of said boundary-scan cells, the stored data being analyzable to isolate the fault.

Claim 3

A boundary-scan tester as recited in claim 1, further comprising: (e) computing means for driving input terminals of the DUT with a series of parallel input vectors and, upon a fault being indicated by said failure signal, computing a vector number identifying the particular input and output vectors present on the terminals of the DUT.

Claim 4

A boundary-scan tester as recited in claim 2, wherein said control means further repeats a boundary-scan test, upon a fault being indicated by said failure signal, up to the last vector in the vector frame present when said fault was indicated.

Claim 5

A boundary-scan tester as recited in claim 1, further comprising: (e) second control means, coupled to said comparing means, for providing said comparing means with said expected output vector.

Claim 6

A boundary-scan tester as recited in claim 1, wherein said control means comprises a microprocessor.

Claim 7

A boundary-scan tester as recited in claim 1, wherein said storage means comprises a RAM.

Claim 8

A boundary-scan tester as recited in claim 1, wherein said driver/receiver means comprises a vector formatter, a driver and receiver.

Claim 9

A boundary-scan tester as recited in claim 7, wherein said vector formatter comprises a Hewlett Packard part number HP 1SG80076 format chip.

Claim 10

A boundary-scan tester as recited in claim 7, wherein said driver comprises a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid.

Claim 11

A boundary-scan tester as recited in claim 7, wherein said receiver comprises a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid.

Claim 12

A boundary-scan tester for diagnosing a fault in a device under test (DUT), the DUT having boundary-scan cells coupled to respective input and output terminals thereof, comprising: (a) driver/receiver means for driving input terminals of the DUT with a parallel input vector and receiving a parallel output vector from output terminals of the DUT; (b) comparing means, coupled to said driver/receiver means, for comparing said output vector with an expected output vector and providing a failure signal indicative of the result thereof and defining a fault; (c) first control means, coupled to said driver/receiver means and said comparing means, for receiving said failure signal from said comparing means and in response thereto transmitting control signals to the DUT via said driver/receiver means, said control signals causing data captured by boundary-scan cells associated with the respective input and output terminals of the DUT to be serially shifted out to said driver/receiver means; (d) storage means, coupled to said driver/receiver means, for storing said input and output vectors and the data shifted out of said boundary-scan cells, the stored data being analyzable to isolate the fault; (e) computing means for driving input terminals of the DUT with a series of parallel input vectors and, upon a fault being indicated by said failure signal, computing a vector number identifying the last vector in a vector frame present on the terminals of the DUT; (f) repeating means, coupled to said control means, for repeating a boundary-scan test, upon a fault being indicated by said failure signal, up to the last vector in a vector frame present when said fault was indicated; and (g) second control means, coupled to said comparing means, for providing said comparing means with said expected output vector.

Claim 13

A boundary-scan tester for diagnosing a fault in a device under test (DUT), the DUT having boundary-scan cells coupled to respective input and output terminals thereof, comprising: (a) driver/receiver means for driving input terminals of the DUT with a parallel input vector and receiving a parallel output vector from output terminals of the DUT; (b) comparing means, coupled to said driver/receiver means, for comparing said output vector with an expected output vector and providing a failure signal indicative of the result thereof and defining a fault; (c) first control means, coupled to said driver/receiver means and said comparing means, for receiving said failure signal from said comparing means and in response thereto transmitting control signals to the DUT via said driver/receiver means, said control signals causing data captured by boundary-scan cells associated with the respective input and output terminals of the DUT to be serially shifted out to said driver/receiver means; (d) storage means, coupled to said driver/receiver means, for storing said input and output vectors and the data shifted out of said boundary-scan cells, the stored data being analyzable to isolate the fault; (e) computing means for driving input terminals of the DUT with a series of parallel input vectors and, upon a fault being indicated by said failure signal, computing a vector number identifying the last vector in a vector frame present on the terminals of the DUT; (f) repeating means, coupled to said control means, for repeating a boundary-scan test, upon a fault being indicated by said failure signal, up to the last vector in a vector frame present when said fault was indicated; and (g) second control means, coupled to said comparing means, for providing said comparing means with said expected output vector.

Claim 14

A boundary-scan tester as recited in claim 11, wherein said control means comprises a microprocessor.

Claim 15

A boundary-scan tester as recited in claim 11, wherein said storage means comprises a RAM.

Claim 16

A boundary-scan tester as recited in claim 11, wherein said driver/receiver means comprises a vector formatter, a driver and receiver.

Claim 17

A boundary-scan tester as recited in claim 14, wherein said vector formatter comprises a Hewlett Packard part number HP 1SG80076 format chip.

Claim 18

A boundary-scan tester as recited in claim 14, wherein said driver comprises a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid.

Claim 19

A boundary-scan tester as recited in claim 14, wherein said receiver comprises a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid.

Claim 20

A boundary-scan tester for diagnosing a fault in a device under test (DUT), the DUT having boundary-scan cells coupled to respective input and output terminals thereof, comprising: (a) driver/receiver means, comprises a vector formatter, a driver and receiver, for driving input terminals of the DUT with a parallel input vector and receiving a parallel output vector from output terminals of the DUT, said vector formatter comprising a Hewlett Packard part number HP 1SG80076 format chip, and including means for comparing said output vector with an expected output vector and providing a failure signal indicative of the result thereof, said driver and receiver comprising a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid; (b) control means, coupled to said driver/receiver means, for receiving said failure signal and in response thereto transmitting control signals to the DUT via said driver/receiver means, said control signals causing data captured by boundary-scan cells associated with the respective input and output terminals of the DUT to be serially shifted out to said driver/receiver means, said control means comprising a microprocessor and means for providing said comparing means with said expected output vector; (c) storing means comprising a RAM, coupled to said driver/receiver means, for storing said input and output vectors and said serial boundary-scan cell data, wherein the stored data may be analyzed to isolate the fault; (d) computing means for driving input terminals of the DUT with a series of parallel input vectors and, in response to said failure signal indicating a fault, computing a vector number identifying a last vector in a vector frame present on the terminals of the DUT; and (e) repeating means, coupled to said control means, for repeating a boundary-scan test, upon a fault being indicated by said failure signal, up to the last vector in the vector frame present when the fault was indicated.

Claim 21

A boundary-scan tester for diagnosing a fault in a device under test (DUT), the DUT having boundary-scan cells coupled to respective input and output terminals thereof, comprising: (a) driver/receiver means, comprises a vector formatter, a driver and receiver, for driving input terminals of the DUT with a parallel input vector and receiving a parallel output vector from output terminals of the DUT, said vector formatter comprising a Hewlett Packard part number HP 1SG80076 format chip, and including means for comparing said output vector with an expected output vector and providing a failure signal indicative of the result thereof, said driver and receiver comprising a Hewlett Packard part number HP 03066-66561 driver/receiver hybrid; (b) control means, coupled to said driver/receiver means, for receiving said failure signal and in response thereto transmitting control signals to the DUT via said driver/receiver means, said control signals causing data captured by boundary-scan cells associated with the respective input and output terminals of the DUT to be serially shifted out to said driver/receiver means, said control means comprising a microprocessor and means for providing said comparing means with said expected output vector; (c) storing means comprising a RAM, coupled to said driver/receiver means, for storing said input and output vectors and said serial boundary-scan cell data, wherein the stored data may be analyzed to isolate the fault; (d) computing means for driving input terminals of the DUT with a series of parallel input vectors and, in response to said failure signal indicating a fault, computing a vector number identifying a last vector in a vector frame present on the terminals of the DUT; and (e) repeating means, coupled to said control means, for repeating a boundary-scan test, upon a fault being indicated by said failure signal, up to the last vector in the vector frame present when the fault was indicated.

Claim 24

A method of diagnosing a fault in a DUT as recited in claim 19, further comprising the step of computing, upon detection of a fault, a vector number identifying the last vector in a vector frame present on the terminals of the DUT at the time the fault was detected.

Claim 25

A method of diagnosing a fault in a DUT as recited in claim 19, further comprising the step of repeating the boundary-scan test, upon the detection of a fault, up to the last vector in a vector frame present at the time the fault was detected.

Claim 26

A method of diagnosing a fault in a DUT as recited in claim 19, further comprising the step of determining said expected output vector prior to performing step (b).

Claim 27

A method of diagnosing a fault in a DUT as recited in claim 19, further comprising the steps of: (i) computing, upon detection of a fault, a vector number identifying the last vector in a vector frame present on the terminals of the DUT at the time the fault was detected; (ii) repeating the boundary-scan test, upon the detection of a fault, up to the last vector in the vector frame present at the time the fault was detected; and (iii) determining said expected output vector prior to performing step (b).