US5023875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlaced scan fault detection system
Assignee: Raytheon Co
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Filing: 1989-05-26
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Granted: 1991-06-11
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Expires: 2009-05-26
Abstract
Abstract A fault detection system 50 includes first and second serial data shift register stages 74, 94 which are connected to a logic circuit under test 106, and a third serial data shift register stage 84 which is logically connected between the first and second serial data sift register stages 74, 94. The fault detection system 50 permits all paths of the logic circuit under test 106 to be sensitized and allows for the detection of all propagation delay type faults at substantially the operational speed of the logic circuit under test 106.
Inventors
- 👤 Gene W. Lee
- 👤 George D. Underwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:53
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858; G01R31/318566
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
187 words
A circuit for facilitating fault detection in testing a logic circuit, comprising: (a) first serial data shift register means for storing and transferring test data, said first serial data shift register means having an input and an output; (b) first means for transferring said tests data from said first serial data shift register means to said logic circuit; (c) second serial data shift register means for storing and transferring said test data, said second serial data shift register means having an input and an output; (d) second means for transferring said test data from said second serial data shift register means to said logic circuit; and (e) third serial data shift register means for storing and transferring said test data, having an input and an output wherein said input is coupled to said output of said first serial data shift register means and said output is coupled to the input of said second serial data shift register means, whereby said logic circuit is enabled to be tested at its normal operating speed such that substantially all of the propagation defaults associated with said logic may be detected.
Claim 2
Dependent Claim
187 words
A circuit for facilitating fault detection in testing a logic circuit, comprising: (a) first serial data shift register means for storing and transferring test data, said first serial data shift register means having an input and an output; (b) first means for transferring said tests data from said first serial data shift register means to said logic circuit; (c) second serial data shift register means for storing and transferring said test data, said second serial data shift register means having an input and an output; (d) second means for transferring said test data from said second serial data shift register means to said logic circuit; and (e) third serial data shift register means for storing and transferring said test data, having an input and an output wherein said input is coupled to said output of said first serial data shift register means and said output is coupled to the input of said second serial data shift register means, whereby said logic circuit is enabled to be tested at its normal operating speed such that substantially all of the propagation defaults associated with said logic may be detected.
Claim 3
Dependent Claim
88 words
The circuit of claim 1 which further comprises data multiplexing means for selecting data, said data multiplexing means having a plurality of inputs, an output and a mode select port; and wherein one of said outputs of said first, second, or third serial data shift register means and said test data are coupled to said input of said data multiplexing means and wherein said output of said data multiplexing means is coupled to one of said inputs of said first, second, and third serial data shift register means.
Claim 4
Dependent Claim
83 words
The circuit of claim 2 wherein an input of said data multiplexing means is also coupled to an operational data signal associated with said logic circuit and wherein, said mode select port of said data multiplexing means is coupled to a mode select signal such that said mode select signal forces said output of said data multiplexing means to be substantially similar to either said operation data signal or to said output of said first, second, or third serial data shift register means.
Claim 5
Dependent Claim
35 words
The circuit of claim 1, wherein said logic circuit is comprised of a plurality of signal paths and wherein said test data is selected such that any of said signal paths may be path sensitized.
Claim 6
Dependent Claim
181 words
In a system for detecting faults associated with a logic circuit, the improvement comprising: (a) first serial data shift register means for storing and transferring test data, said first serial data register means having an input and an output; (b) first means for transferring said tests data from said first serial data shift register means to said logic circuit; (c) second serial data shift register means for storing and transferring said test data, said second serial data shift register means having an input and an output; (d) second means for transferring said test data from said second serial data shift register means to said logic circuit; (e) third serial data shift register means for storing and transferring said test data, having an input and an output wherein said input is coupled to said output of first serial data shift register means and said output is coupled to the input of said second serial data shift register means, whereby said logic circuit is enabled to be tested at its normal operating speed such that substantially all propagation delay faults may be detected.
Claim 7
Dependent Claim
181 words
In a system for detecting faults associated with a logic circuit, the improvement comprising: (a) first serial data shift register means for storing and transferring test data, said first serial data register means having an input and an output; (b) first means for transferring said tests data from said first serial data shift register means to said logic circuit; (c) second serial data shift register means for storing and transferring said test data, said second serial data shift register means having an input and an output; (d) second means for transferring said test data from said second serial data shift register means to said logic circuit; (e) third serial data shift register means for storing and transferring said test data, having an input and an output wherein said input is coupled to said output of first serial data shift register means and said output is coupled to the input of said second serial data shift register means, whereby said logic circuit is enabled to be tested at its normal operating speed such that substantially all propagation delay faults may be detected.
Claim 8
Dependent Claim
88 words
The improvement of claim 5 which further comprises data multiplexing means for selecting data, said data multiplexing means having a plurality of inputs, an output, and a mode select port; and wherein one of said outputs of said first, second, or third serial data shift register means and said test data are coupled to said input of said data multiplexing means and wherein said output of said data multiplexing means is coupled to one of said inputs of said first, second and third serial data shift register means.
Claim 9
Dependent Claim
78 words
The improvement of claim 6 wherein said input of said data multiplexing means is also coupled to an operational data signal associated with said logic circuit and wherein, said mode select port is coupled to a mode select signal such that said mode select signal forces said output of said data multiplexing means to be substantially similar to either said operational data signal or to said output of said first, second, or third serial data shift register means.
Claim 10
Independent Claim
261 words
A method for detecting faults associated with a logic circuit, wherein said fault detection may occur at the normal operating speed of said logic circuit such that substantially all of the propagation delay faults of said logic circuit may be detected, wherein said method comprises: (a) providing a first serial data shift register means for storing and transferring test data to said logic circuit, wherein said first serial data shift register means has an input and output and said logic circuit has an output; (b) providing a second serial data shift register means for storing and transferring said test data to said logic circuit, wherein said second serial data shift register means has an input and output; (c) coupling a third serial data shift register means for storing and transferring said test data, having an input and output, to said first and second serial data shift register means such that the output of said third serial data shift register means is coupled to the input of said second serial data shift register means and the input of said third serial data shift register means is coupled to the output of said first serial data shift register means; (d) inputting said test data to said first serial data shift register means; (e) shifting said input data, one bit at a time, through said first, second, and third serial data shift register means while transferring the bits in the first and second data shift register means to the logic circuit; and (f) monitoring said output of said logic circuit to detect said fault.
Claim 11
Independent Claim
261 words
A method for detecting faults associated with a logic circuit, wherein said fault detection may occur at the normal operating speed of said logic circuit such that substantially all of the propagation delay faults of said logic circuit may be detected, wherein said method comprises: (a) providing a first serial data shift register means for storing and transferring test data to said logic circuit, wherein said first serial data shift register means has an input and output and said logic circuit has an output; (b) providing a second serial data shift register means for storing and transferring said test data to said logic circuit, wherein said second serial data shift register means has an input and output; (c) coupling a third serial data shift register means for storing and transferring said test data, having an input and output, to said first and second serial data shift register means such that the output of said third serial data shift register means is coupled to the input of said second serial data shift register means and the input of said third serial data shift register means is coupled to the output of said first serial data shift register means; (d) inputting said test data to said first serial data shift register means; (e) shifting said input data, one bit at a time, through said first, second, and third serial data shift register means while transferring the bits in the first and second data shift register means to the logic circuit; and (f) monitoring said output of said logic circuit to detect said fault.
Claim 12
Dependent Claim
39 words
The method of claim 8, wherein said method further comprises connecting a plurality of multiplexers between the first, second and third shift registers; and using the multiplexers to selectively couple test data or operational data to the shift registers.
Claim 13
Dependent Claim
37 words
The method of claim 9, wherein said logic circuit includes at least one AND gate having two inputs and wherein the first and second data shift registers provide test signals substantially simultaneously to the AND gate inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |