Functional test method for asynchronous sequential circuits
Abstract
Abstract A METHOD FOR TESTING PHYSICAL SEQUENTIAL LOGIC CIRCUITS INCLUDING A PROGRAM STEP FOR CONTROLLING A COMPUTER TO GENERATE TEST PATTERNS FOR USE IN LOCATING PERMANENT FAULTS IN PHYSICAL SEQUENTIAL LOGIC CIRCUITS BUILT FOR USE IN DIGITAL EQUIPMENT BY PROVIDING A METHOD FOR FINDING FEEDBACK LOOPS AND IDENTIFYING AN APPROPRIATE LINE IN THE LOOP TO TERNS, AND APPLYING THE TEST PATTERNS TO THE PHYSICAL SEQUENTIAL CIRCUIT. CUT, AT LEAS FIGURATIVELY, IN ORDER TO CONVERT A REPRESENTATION OF THE PHYSICAL SEQUENTIAL CIRCUIT TO A REPRESENTATION OF AN EQUIVALENT COMBINATIONAL CIRCUIT, ANALYZING THE RESULTANT COMBINATION CIRCUIT REPRESENTATION ACCORDING TO SPECIFIC BOOLEAN RULES TO OBTAIN A COMPLETE SET OF TEST PAT- D R A W I N G
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