Comparison circuit for masking transient differences

Claim 2

A comparison circuit for comparing first and second binary signals which are transmitted to said comparison circuit, said comparison circuit comprising: delay means which recieves the first and second signals transmitted to the comparison circuit and delays the further transmission of the first and second signals for a predetermined time interval "d"; and comparison means, coupled to the delay means, for comparing the first and second binary signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another.

Claim 3

A comparison circuit as in claim 1, wherein said comparison means is constructed exclusively from synchronously operating circutry.

Claim 4

A comparison circuit as in claim 1, comprising first and second inputs for each of the first and second signals, the first inputs of the first and second signals being fed into said delay means for forming versions of the first and second signals respectively delayed by the time interval, said delay means having respective first and second outputs for the respective first and second delayed versions of the signals, and said comparision means further comprising gate means having four inputs respectively fed by the first and second inputs and by the first and second outputs for forming at an output of said gate means the non-correspondence signal.

Claim 5

A comparison circuit as in claim 3, wherein said gate means comprises a first comparison gate means fed by the four inputs for detecting when any of the first signal, the delayed version of the first signal, the inverse of the second signal, and the inverse of the delayed version of the second signal has a predetermined logic state, a second comparison gate means fed by the four inputs for detecting when any of the second signal, the delayed version of the second signal, the inverse of the first signal, and the inverse of the delayed version of the first signal has the predetermined logic state, and said gate means further comprises a combining gate means fed by the outputs of said first and second comparison gate means, for forming the non-correspondence signal when neither said first nor said second comparison gate means detects the predetermined logic state.

Claim 6

A comparison circuit as in claim 3, wherein said gate means comprises first, second, third, and fourth two-input comparison gate means, said first comparison gate means fed for detecting whether the logic states of the first signal and delayed version of the second signal are the same or different, said second comparison gate means fed for detecting whether the logic states of the second signal and the delayed version of the first signal are the same or different, said third gate comparison means fed for detecting whether the logic states of the delayed versions of the first and second signals are the same or different, said fourth comparison gate means fed for detecting whether the logic states of the first and second signals are the same or different, and said gate means further comprises a combining gate means fed by outputs of said first, second, third and fourth comparison gate means for forming the non-correspondence signal when any of said first, second, third, and fourth comparison gate means detects different logic states.

Claim 7

A comparison circuit system for comparing a plurality of sets of first and second binary signals which are transmitted to said system, said system comprising: a plurality of comparison circuits each of which is for comparing a given set of first and second binary signals; delay means which recieves the first and second signals transmitted to each of said comparison circuits and delays the further transmission of the first and second signals for a predetermined time interval "d"; comparison means, coupled to the delay means, for comparing the first and second binary signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another; and general combination gate means for receiving the outputs of each of the comparison circuits, said combination gate means outputting a non-correspondence signal if any of the comparison circuits output a non-correspondence signal.

Claim 8

A comparison circuit system for comparing a plurality of sets of first and second binary signals which are transmitted to said system, said system comprising: a plurality of comparison circuits each of which is for comparing a given set of first and second binary signals; delay means which recieves the first and second signals transmitted to each of said comparison circuits and delays the further transmission of the first and second signals for a predetermined time interval "d"; comparison means, coupled to the delay means, for comparing the first and second binary signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another; and general combination gate means for receiving the outputs of each of the comparison circuits, said combination gate means outputting a non-correspondence signal if any of the comparison circuits output a non-correspondence signal.

Claim 9

The comparison circuit system as in claim 6, wherein each of said comparison circuits comprises first and second inputs for each of the first and second signals, the first inputs of the first and second signals being fed into said delay means for forming delayed versions of the first and second signals respectively, said delay means having respective first and second outputs for the respective first and second delayed versions of the signals, and said comparision means comprsing gate means having four inputs respectively fed by the first and second inputs and by the delayed versions of the first and second signals, said gate means outputting the non-correspondence signal.

Claim 10

The comparison circuit system as in claim 7, wherein said gate means comprises a first comparison gate means fed by the four inputs for detecting when any of the first signal, the delayed version of the first signal, the inverse of the second signal, and the inverse of the delayed version of the second signal has a predetermined logic state, a second comparison gate means fed by the four inputs for detecting when any of the second signal, the delayed version of the second signal, the inverse of the first signal, and the inverse of the delayed version of the first signal has the predetermined logic state, and said gate means further comprises a combining gate means fed by the outputs of said first and second comparison gate means, for forming the non-correspondence signal when neither said first nor said second comparison gate means detects the predetermined logic state.

Claim 11

The comparison circuit system as in claim 7, wherein said gate means comprises first, second, third, and fourth two-input comparison gate means, said first comparison gate means fed for detecting whether the logic states of the first signal and delayed version of the second signal are the same or different, said second comparison gate means fed for detecting whether the logic states of the second signal and the delayed version of the first signal are the same or different, said third gate comparison means fed for detecting whether the logic states of the delayed versions of the first and second signals are this same or different, said fourth comparison gate means fed for detecting whether the logic states of the first and second signals are this same or different, and said gate means further comprises a combining gate means fed by outputs of said first, second, third and fourth comparison gate means for forming the signal when any of said first, second, third, and fourth comparison gate means detects different logic states.

Claim 12

The comparison circuit system as in claim 6, wherein said general combination gate means comprises an OR gate.

Claim 13

A processing system for receiving a binary signal input, processing the signal, and providing a signal output, said processing system comprising: input signal means; first and second processing means, both of which are coupled to the input signal means, and both of which process the signal and respectively output a first processed signal and a second processed signal; delay means coupled to said first and second processing means for delaying the transmission of the first and second signal a predetermined time interval "d" after the transmission of the first and second processed signals by the first and second processing means; and comparison means for comparing the first and second processed signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another.

Claim 14

A processing system for receiving a binary signal input, processing the signal, and providing a signal output, said processing system comprising: input signal means; first and second processing means, both of which are coupled to the input signal means, and both of which process the signal and respectively output a first processed signal and a second processed signal; delay means coupled to said first and second processing means for delaying the transmission of the first and second signal a predetermined time interval "d" after the transmission of the first and second processed signals by the first and second processing means; and comparison means for comparing the first and second processed signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another.

Claim 15

A processing system as in claim 11, wherein said processing means operate in mutual synchronism.

Claim 16

A processing system as in claim 11, wherein said processing means operate mutually asynchronously.

Claim 17

The processing system as in claim 11, wherein said comparison means comprises first and second inputs for each of the first and second signals, the first inputs of the first and second signals being fed into said delay means for forming delayed versions of the first and second signals respectively, said delay means having respective first and second outputs for the respective first and second delayed versions of the signals, and said comparison further comprises gate means having four inputs respectively fed by the first and second inputs and by the delayed versions of the first and second signals, said gate means outputting the non-correspondence signal.

Claim 18

The processing system as in claim 14, wherein said gate means comprises a first comparison gate means fed by the four inputs for detecting when any of the first signal, the delayed version of the first signal, the inverse of the second signal, and the inverse of the delayed version of the second signal has a predetermined logic state, a second comparison gate means fed by the four inputs for detecting when any of the second signal, the delayed version of the second signal, the inverse of the first signal, and the inverse of the delayed version of the first signal has the predetermined logic state, and said gate means further comprises a combining gate means fed by the outputs of said first and second comparison gate means, for forming the non-correspondence signal when neither said first nor said second comparison gate means detects the predetermined logic state.

Claim 19

The processing system as in claim 14, wherein said gate means comprises first, second, third, and fourth two-input comparison gate means, said first comparison gate means fed for detecting whether the logic states of the first signal and delayed version of the second signal are the same or different, said second comparison gate means fed for detecting whether the logic states of the second signal and the delayed version of the first signal are the same or different, said third gate comparison means fed for detecting whether the logic states of the delayed versions of the first and second signals are this same or different, said fourth comparison gate means fed for detecting whether the logic states of the first and second signals are the same or different, and said gate means further comprises a combining gate means fed by outputs of said first, second, third and fourth comparison gate means for forming the signal when any of said first, second, third, and fourth comparison gate means detects different logic states.

Claim 20

The processing system as in claim 11, further comprising output gating means for inhibiting the transmission of the first processed signal in the event that the comparison means outputs a non-correspondence signal, said comparison means being coupled to the output gating means.