US3810119A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor synchronization scheme
Assignee: United States Department of the Navy
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Filing: 1971-05-04
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Granted: 1974-05-07
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Expires: 1991-05-04
Abstract
Abstract A method of maintaining synchronization between two independently clocked, stored-program computer processors which are executing the same program simultaneously and are connected in a master-slave relationship. There is further provided a method of preventing a failure from disabling both master and slave units. A special function is inserted at selected intervals which delays the master processor until the slave processor catches up. Further, means are provided to automatically detect when a failure occurs. This program alignment and error detection are accomplished by inserting checkpoints at selected intervals at which the redundantly processed results are compared.
Inventors
- 👤 R Zieve
- 👤 C Maginnis
- 👤 M Kleidermacher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1641; G06F11/165; G06F11/1675; G06F11/1683; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30087; G06F9/38; G06F9/3836
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
172 words
A method of maintaining synchronization between an on-line, stored-program computer-processor and an independently clocked, off-line, stored-program computer-processor which are executing the same program simultaneously comprising the steps of: inserting at predetermined points in the program MAT instructions; generating in each processor an RTS signal when a MAT instruction is reached; timing the period between the generation of an RTS signal by one of said processors and the generation of an RTS signal by the other of said processors; determining whether this period between RTS signals exceeds a predetermined period; permitting the processor that generated the first RTS signal to proceed independently through the main program ignoring all MAT instructions of the other processor does not generate an RTS signal within this predetermined period; determing whether both of said processors have reached the same point in the program by determining whether or not both of the RTS signals are present simultaneously within this predetermined period; and, permitting both of the processors to resume the program only if both RTS signals are present simultaneously.
Claim 2
Independent Claim
172 words
A method of maintaining synchronization between an on-line, stored-program computer-processor and an independently clocked, off-line, stored-program computer-processor which are executing the same program simultaneously comprising the steps of: inserting at predetermined points in the program MAT instructions; generating in each processor an RTS signal when a MAT instruction is reached; timing the period between the generation of an RTS signal by one of said processors and the generation of an RTS signal by the other of said processors; determining whether this period between RTS signals exceeds a predetermined period; permitting the processor that generated the first RTS signal to proceed independently through the main program ignoring all MAT instructions of the other processor does not generate an RTS signal within this predetermined period; determing whether both of said processors have reached the same point in the program by determining whether or not both of the RTS signals are present simultaneously within this predetermined period; and, permitting both of the processors to resume the program only if both RTS signals are present simultaneously.
Claim 3
Dependent Claim
32 words
The method of claim 1 further comprising the step of delaying, if the RTS signal from one of the processors is absent, the other processor until both RTS signals are present simultaneously.
Claim 4
Dependent Claim
46 words
The method of claim 2 further comprising the steps of: transferring to a comparator predetermined data from each processor when a MAT instruction is reached; comparing the data; and, permitting the processors to resume the program only if the data from each processor is the same.
Claim 5
Dependent Claim
34 words
The method of claim 3 further comprising the step of switching the processors to an error detection program if the data from each processor is not the same and both RTS signals are present.
Claim 6
Dependent Claim
27 words
The method of claim 3 further comprising the step of delaying the off-line processor from resuming the program until after the on-line processor has resumed the program.
Claim 7
Dependent Claim
62 words
The method of claim 3 further comprising the steps of: subjecting the processors to a hardware interrupt cycle, the occurrence of which is asynchronous with respect to program execution; comparing the number of instructions executed by the processors; and, allowing the off-line processor to enter the interrupt cycle only when it has executed the same number of instructions as the on-line processor.
Claim 8
Dependent Claim
74 words
The method of claim 6 wherein the step of comparing the number of instructions executed by the processors includes the steps of: counting in a first binary counter the number of instructions executed by the on-line processor; counting in a second binary counter the number of instructions executed by the off-line processor; comparing the count in the first and second binary counters; and, generating a COUNT EQUAL signal when the counts are the same.
Claim 9
Dependent Claim
24 words
The method of claim 7 further comprising the step of resetting the first and second counters to zero when a MAT instruction is reached.
Claim 10
Dependent Claim
21 words
The method of claim 7 further comprising the step of delaying the off-line processor when a COUNT EQUAL signal is present.
Claim 11
Dependent Claim
28 words
The method of claim 7 further comprising the step of delaying the on-line processor if, upon completion of an interrupt cycle, a COUNT EQUAL signal is not present.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-06 | 1977-11-05 | 1978-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-06 | 1981-11-05 | 1982-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-06 | 1985-11-05 | 1986-05-07 | $7700.00 | Window Closed / Lapsed |