Multiprocessor with cooperative program execution

Claim 2

In combination, a plurality of data processors, each comprising means for selectively obtaining program instructions from memory in accordance with address information, an instruction register for storing instructions selectively obtained from memory, internal decoder means for decoding instructions stored in said instruction register, execution means controlled by said internal decoder means in accordance with an instruction stored in said instruction register for performing a set of logic functions specified by said instruction; external decoder means in one of said processors for decoding instructions stored in said instruction register of another of said processors; and said execution means of said one processor controlled by said external decoder in accordance with said instruction stored in said instruction register of said other processor for performing a set of logic functions specified by said instruction.

Claim 3

The combination according to claim 1 wherein said set of logic functions performed by said execution means of said one processor under control of said external decoder means of said one processor is different from said set of logic functions performed by said execution means of said other processor under control of said internal decoder means of said other processor.

Claim 4

The combination according to claim 2 wherein said execution means of said one and said other processors are connected by gating elements selectively controlled by said execution means of said one and said other processors, and said sets of logic functions comprise transfers of information between said execution means of said one and said other processors through said gating elements.

Claim 5

The combination according to claim 1 wherein said one processor comprises inhibiting means controlled by said execution means of said one processor for inhibiting said internal decoder means of said one processor, and said set of logic functions performed in said one processor comprises activation of said inhibiting means by said execution means.

Claim 6

The combination according to claim 1 wherein said one processor comprises inhibiting means controlled by said execution means of said one processor for inhibiting said internal decoder means of said one processor, and said set of logic functions performed in said one processor comprises deactivation of said inhibiting means by said execution means of said one processor.

Claim 7

The combination according to claim 1 wherein said execution means of each of said processors comprises means for clearing information from data storage elements in said execution means, said one processor comprises inhibiting means for inhibiting activation of said clearing means of said one processor, and said set of logic functions performed in said one processor comprises activation of said inhibiting means by said execution means of said one processor.

Claim 8

The combination according to claim 1 wherein said execution means of each of said processors comprises means for clearing information from data storage elements in said execution means, said one processor comprises inhibiting means for inhibiting activation of said clearing means of said one processor, and said set of logic functions performed in said one processor comprises deactivation of said inhibiting means by said execution means of said one processor.

Claim 9

The combination according to claim 1 wherein said program instruction obtaining meAns of each of said processors is controlled by said execution means of said processor in accordance with address information stored in said execution means of said processor, and said set of logic functions performed in said one processor comprises the control by said execution means of said one processor of said program instruction obtaining means of said one processor for obtaining from memory an instruction having a memory address defined by address information stored in said execution means of said one processor and storing said obtained instruction in said instruction register means of said one processor.

Claim 10

The combination according to claim 1 wherein said execution means of each of said processors comprises a plurality of registers and functional circuits and transmission means for transferring information between selected of said registers and functional circuits under control of said execution means in accordance with said instruction, said transmission means of said one and said other processors are interconnected by controllable gating elements controlled by said execution means of said one and said other processors, said set of logic functions performed in said other processor comprises transfer of information from a selected register in said other processor specified in said instruction to said transmission means of said other processor, and said set of logic functions performed in said one processor comprises the transfer of information through said gating elements from said transmission means of said other processor to a selected register in said one processor specified in said instruction.

Claim 11

The combination according to claim 9 wherein said selected register in said one processor comprises an address register which controls said program instruction obtaining means of said one processor by defining the memory address from which an instruction is obtained.

Claim 12

The combination according to claim 9 wherein said one processor comprises means controlled by said execution means of said one processor for transferring information from said transmission means of said one processor to said instruction register of said one processor, and said selected register in said one processor comprises said instruction register of said one processor.

Claim 13

The combination according to claim 1 wherein said execution means of said one processor comprises data storage means, address storage means for storing said address information for said one processor, clearing means for selectively clearing data from said data storage means and address information from said address storage means, means for inhibiting said clearing means and said internal decoding means of said one processor, means for transferring information selectively between said data storage means, said address storage means, and said instruction register of said one processor; said execution means of said other processor is connected through controllable gating elements to said transferring means in said one processor; and said external decoder means controls said execution means of said one processor in accordance with a sequence of instructions selectively obtained from memory by said other processor and sequentially stored in said instruction register of said other processor to selectively activate and deactivate said inhibiting means, said transferring means, and said gating elements so as to control said one processor in executing a particular instruction or sequence of instructions defined by information transferred from said other processor in a step-by-step manner.

Claim 14

In combination, memory means for storing instructions defining data processing functions; a pair of data processors, each comprising an instruction register for storing an instruction obtained from memory by said processor, a plurality of registers and processing circuits, transmission means for selectively interconnecting said plurality oF registers and processing circuits for data transfer therebetween, gating means for transferring data between said transmission means and the transmission means of the other processor, decoder means connected to said instruction register and to the instruction register of the other processor for identifying the functions defined by the instruction stored in one of said instruction registers, and logic control means controlled by said decoder means for controlling selectively said transmission means, said processing circuits, and said gating means to execute said identified functions.

Claim 15

In combination, memory means for storing instructions defining data processing functions; a pair of data processors, each comprising an instruction register for storing an instruction obtained from memory by said processor, a plurality of registers and processing circuits, transmission means for selectively interconnecting said plurality oF registers and processing circuits for data transfer therebetween, gating means for transferring data between said transmission means and the transmission means of the other processor, decoder means connected to said instruction register and to the instruction register of the other processor for identifying the functions defined by the instruction stored in one of said instruction registers, and logic control means controlled by said decoder means for controlling selectively said transmission means, said processing circuits, and said gating means to execute said identified functions.

Claim 16

The combination according to claim 13 wherein each of said processors comprises inhibit means connected to said logic control means for inhibiting a portion of said decoder means of one of said processors and for inhibiting clearance of information from said registers in said one processor, said logic control means of said one processor controlled by the active portion of said decoder means of said one processor for controlling the execution of a function identified by an instruction stored in said instruction register of the other processor, and said logic control means of said other processor controlled by said decoder means of said other processor for controlling the execution of a function identified by said instruction stored in said instruction register of said other processor.

Claim 17

In combination, memory means for storing instructions defining data processing functions; first and second data processors, each comprising a plurality of registers and processing circuits, transmission means for selectively interconnecting said plurality of registers and processing circuits for data transfer therebetween, gating means for transferring data between said transmission means and the transmission means of the other processor; said first processor comprising a first instruction register for storing an instruction obtained by said first processor from said memory means, first decoder means connected to said first instruction register for identifying the functions defined by said instruction stored in said first instruction register, first logic control means connected to and controlled by said first decoder means for controlling selectively said transmission means, said processing circuits and said gating means in said first processor to execute said identified function in said first processor; said second processor comprising second decoder means connected to said first instruction register for identifying other functions defined by said instruction stored in said first instruction register, and second logic control means connected to and controlled by said second decoder means for controlling selectively said transmission means, said processing circuits and said gating means in said second processor to execute said identified other functions in said second processor.

Claim 18

In combination, memory means for storing instructions defining data processing functions; first and second data processors, each comprising a plurality of registers and processing circuits, transmission means for selectively interconnecting said plurality of registers and processing circuits for data transfer therebetween, gating means for transferring data between said transmission means and the transmission means of the other processor; said first processor comprising a first instruction register for storing an instruction obtained by said first processor from said memory means, first decoder means connected to said first instruction register for identifying the functions defined by said instruction stored in said first instruction register, first logic control means connected to and controlled by said first decoder means for controlling selectively said transmission means, said processing circuits and said gating means in said first processor to execute said identified function in said first processor; said second processor comprising second decoder means connected to said first instruction register for identifying other functions defined by said instruction stored in said first instruction register, and second logic control means connected to and controlled by said second decoder means for controlling selectively said transmission means, said processing circuits and said gating means in said second processor to execute said identified other functions in said second processor.

Claim 19

The combination according to claim 15 wherein said second processor comprises a second instruction register for storing an instruction obtained by said second processor from said memory means, third decoder means connected to said second instruction register for identifying the functions defined by said instruction stored in said second instruction register, said second logic control means connected to and controlled by said third decoder means for controlling selectively said transmission means, said processing circuits and said gating means in said second processor to execute said functions defined by said instruction stored in said second instruction register, inhibit means controlled by said second logic control means for inhibiting control of said second logic control means by said third decoder means, said second decoder means responsive to a specific instruction stored in said first instruction register for controlling said second logic control means to activate said inhibit means.

Claim 20

The combination according to claim 16 wherein said second decoder means is responsive to another specific instruction stored in said first instruction register for controlling said second logic means to selectively operate said transmission means and said gating means of said second processor for transferring data from said transmission means of said first processor to a selected one of said plurality of registers and data processing circuits.

Claim 21

The combination according to claim 17 wherein said second decoder means is responsive to a third specific instruction stored in said first instruction register for controlling said second logic control means to deactivate said inhibit means.