US3634769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sequential gating circuit
Assignee: RELEX CORP
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Filing: 1969-12-12
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Granted: 1972-01-11
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Expires: 1989-12-12
Abstract
Abstract A gating circuit for sequentially initiating a plurality of different processes or events in accordance with a predetermined preferential sequence of activation. A plurality of gates are provided, each of which receives an independent input signal for initiating the corresponding process or event. The output signal of each gate circuit is fed back to all of the other gate circuits as an inhibiting signal to prevent any two of the gates from being activated at the same time. The inhibiting signals are applied to the other gates through a plurality of different delay lines which establish a preferential time sequence of gate activation. When one gate has been activated, it inhibits all of the other gates until the corresponding process or event has been completed, at which time the inhibiting signal to the other gates is removed. Due to the difference in delay time, however, the removal of the inhibiting signal occurs in a time sequence which establishes a preferential sequence of gate activation for the remaining gates.
Inventors
- 👤 Roland G Sleater
- 👤 Charles G Reed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:29
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/002; G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/07; G06; G06F; G06F1/00; G06F1/04; G06F1/14; G05B2219/00; G05B2219/20; G05B2219/25; G05B2219/25411
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
209 words
A gating circuit for sequentially initiating a plurality of different processes or events in accordance with a predetermined preferential time sequence, comprising: a plurality of AND gates each having one output and at least two inputs, means for coupling the output of each AND gate to the control means of a corresponding one of said processes for initiating the process, means coupled to a first input of each AND gate for receiving an input signal to activate the corresponding AND gate, and feedback means coupled between the output of each AND gate and a second input of all of the other AND gates, said feedback means being operable when any one of the AND gates is activated to apply inhibiting signals to all of the remaining AND gates to prevent any two of the gates from being activated at the same time, each of said inhibiting signals being applied through time delay means for establishing a predetermined time sequence with respect to the termination of the inhibiting signals, each of said time delay means delaying inhibiting signals passing therethrough for an increment of time differing from that of all other said time delay means thereby establishing a predetermined preferential time sequence of initiation for the corresponding processes or events.
Claim 2
Dependent Claim
209 words
A gating circuit for sequentially initiating a plurality of different processes or events in accordance with a predetermined preferential time sequence, comprising: a plurality of AND gates each having one output and at least two inputs, means for coupling the output of each AND gate to the control means of a corresponding one of said processes for initiating the process, means coupled to a first input of each AND gate for receiving an input signal to activate the corresponding AND gate, and feedback means coupled between the output of each AND gate and a second input of all of the other AND gates, said feedback means being operable when any one of the AND gates is activated to apply inhibiting signals to all of the remaining AND gates to prevent any two of the gates from being activated at the same time, each of said inhibiting signals being applied through time delay means for establishing a predetermined time sequence with respect to the termination of the inhibiting signals, each of said time delay means delaying inhibiting signals passing therethrough for an increment of time differing from that of all other said time delay means thereby establishing a predetermined preferential time sequence of initiation for the corresponding processes or events.
Claim 3
Dependent Claim
119 words
A gating circuit as defined in claim 1 wherein said feedback means includes a plurality of multiple-input OR gates each having one output and a plurality of inputs, the output of each OR gate being coupled to said second input of a corresponding one of said AND gates, means coupling each of said OR gate inputs to the output of a different one of said AND gates, said time delay means each coupled in series with a different input of said OR gates for establishing a predetermined time sequence with respect to the termination of signals applied to the inputs of said OR gates, thereby establishing a predetermined preferential time sequence of activation for the corresponding process or events.
Claim 4
Dependent Claim
106 words
A gating circuit as defined in claim 2 and also including a plurality of flip-flops each having a ''''set'''' input and a ''''reset'''' input and at least one output, the ''''set'''' input of each flip-flop being coupled to the output of a corresponding one of said AND gates, the output of each of said flip-flops being coupled to the control means of a corresponding one of said processes for initiating the process, means coupled to the ''''reset'''' input of each flip-flop for resetting the flip-flop when the corresponding process has been completed and said feedback means being coupled to the output of each of said flip-flops.
Claim 5
Dependent Claim
124 words
A gating circuit as defined in claim 3 and also including a plurality of one-shot multivibrators each having an input and at least one output, each of said one-shot multivibrators being operable when triggered by an input signal to produce an output signal having a time duration which is longer than the longest of said time delay circuits, the input of each one-shot multivibrator being coupled to the output of a corresponding one of said flip-flops, and the output of each one-shot multivibrator being coupled to one input of the corresponding AND gate to inhibit said AND gate for a time delay which is longer than the delay time of the longest of said time delay circuits after the corresponding flip-flop has been reset.
Claim 6
Dependent Claim
30 words
A gating circuit as defined in claim 4 wherein the output of each one-shot multivibrator is coupled to the input of the corresponding AND gate Via the corresponding OR gate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-10 | 1975-07-12 | 1976-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-10 | 1979-07-12 | 1980-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-10 | 1983-07-12 | 1984-01-11 | $7700.00 | Window Closed / Lapsed |