US5550528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matching of digital patterns using analog logic
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-03-01
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Granted: 1996-08-27
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Expires: 2015-03-01
Abstract
Abstract A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.
Inventors
- 👤 Glen E. Offord
- 👤 Jeffrey L. Sonntag
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:50
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
212 words
An integrated circuit comprising circuitry for indicating whether a first set of digital values at least partially matches a second set of digital values to within a desired degree, said circuitry comprising: set of digital comparators each having a first input for connection to a source of said first set of digital values and a second input for connection to a source of said second set of digital values, and an output; and further comprising current sources each connected to an output of a digital comparator for providing a first value of current when a pair of digital values from said first and second sets are equal, and for providing a second value of current when the pair of digital values from said first and second sets are not equal, and a current summer for summing the currents from said current sources to produce a total current; and still further comprises a current comparator that provides a first output signal when said total current exceeds a given value, and provides a second output signal when said total current is less than a given value, wherein said current comparator comprises a current sink that sinks a value of current up to a maximum value, beyond which the voltage across said current sink rises.
Claim 2
Dependent Claim
212 words
An integrated circuit comprising circuitry for indicating whether a first set of digital values at least partially matches a second set of digital values to within a desired degree, said circuitry comprising: set of digital comparators each having a first input for connection to a source of said first set of digital values and a second input for connection to a source of said second set of digital values, and an output; and further comprising current sources each connected to an output of a digital comparator for providing a first value of current when a pair of digital values from said first and second sets are equal, and for providing a second value of current when the pair of digital values from said first and second sets are not equal, and a current summer for summing the currents from said current sources to produce a total current; and still further comprises a current comparator that provides a first output signal when said total current exceeds a given value, and provides a second output signal when said total current is less than a given value, wherein said current comparator comprises a current sink that sinks a value of current up to a maximum value, beyond which the voltage across said current sink rises.
Claim 3
Dependent Claim
18 words
The invention of claim 1 wherein said digital comparators are exclusive OR gates, or alternatively exclusive NOR gates.
Claim 4
Dependent Claim
47 words
The invention of claim 1 wherein said current sources comprise a parallel array of field effect transistors having their gates coupled to the outputs of said digital comparators, and having their sources connected to a voltage source, and having their drains connected together at a common node.
Claim 5
Dependent Claim
33 words
The invention of claim 1 wherein said current sink comprises a proportional current mirror having a reference current flowing in a first branch and having said total current flowing in a second branch.
Claim 6
Dependent Claim
31 words
The invention of claim 1 wherein said second set of digital values is a reference pattern, and said integrated circuit further comprises said source of said second set of digital values.
Claim 7
Independent Claim
174 words
An method for indicating whether a first set of digital values at least partially matches a second set of digital values to within a desired degree, said method comprising: comparing a first set of digital values to a second set of digital values to produce comparison results; controlling current sources by said comparison results to provide a first value of current when a pair of digital values from said first and second sets are equal, and to provide a second value of current when the pair of digital values from said first and second sets are not equal; summing the currents from said current sources to produce a total current; comparing said total current to a given value by means of a current sink that sinks a value of current up to a maximum value, beyond which the voltage across said current sink rises; and providing a first signal when said total current is less than said given value, and providing a second signal when said total current is greater that said given value.
Claim 8
Independent Claim
174 words
An method for indicating whether a first set of digital values at least partially matches a second set of digital values to within a desired degree, said method comprising: comparing a first set of digital values to a second set of digital values to produce comparison results; controlling current sources by said comparison results to provide a first value of current when a pair of digital values from said first and second sets are equal, and to provide a second value of current when the pair of digital values from said first and second sets are not equal; summing the currents from said current sources to produce a total current; comparing said total current to a given value by means of a current sink that sinks a value of current up to a maximum value, beyond which the voltage across said current sink rises; and providing a first signal when said total current is less than said given value, and providing a second signal when said total current is greater that said given value.
Claim 9
Dependent Claim
21 words
The invention of claim 6 wherein said comparing is accomplished by means of exclusive OR gates, or alternatively exclusive NOR gates.
Claim 10
Dependent Claim
47 words
The invention of claim 6 wherein said current sources comprise a parallel array of field effect transistors having their gates coupled to the outputs of said digital comparators, and having their sources connected to a voltage source, and having their drains connected together at a common node.
Claim 11
Dependent Claim
33 words
The invention of claim 6 wherein said current sink comprises a proportional current mirror having a reference current flowing in a first branch and having said total current flowing in a second branch.
Claim 12
Dependent Claim
31 words
The invention of claim 6 wherein said second set of digital values is a reference pattern, and said integrated circuit further comprises said source of said second set of digital values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |