US5140538A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid digital-analog computer parallel processor
Assignee: University of Arkansas at Fayetteville
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Filing: 1988-12-27
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Granted: 1992-08-18
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Expires: 2008-12-27
Abstract
Abstract Hybrid digital-analog computer parallel processing apparatus wherein a template circuit, or multiplicity thereof, is connected to receive parallel digital inputs, each template circuit having controlled current sources with control gates connected respectively to parallel digital inputs. Current sub-sources for each pixel normally have programmable current output and "0" or "1" responses. Each template circuit has a current summing device for algebraically adding the current outputs of current sources, while a greatest value is detected at a comparator which may have a ramp signal applied to another input thereby identifying which template produced a maximum indication from the same parallel inputs. A self-calibrating feedback controlled current generator supplies all current sources on a chip making it possible to generate a known comparator input independent of IC resistivity or other parameters. The value of the indication of other templates may also be determined by the time relation of comparator output signals. If templates of the apparatus represent printed character correlation data, the output of the processor would identify the template with maximum indication and character with highest probability from a set of pixel inputs. Similar apparatus can be cascaded to first identify details in a scene and then match such detail charts with second stage templates.
Inventors
- 👤 J. E. Bass
- 👤 Randy L. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:12
CPC Classifications
G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
519 words
In a hybrid digital-analog computer parallel processor having a multiplicity of digital inputs the improvement comprising: (A) a plurality of template circuits, all the circuit elements of at least one complete template circuit being on a single integrated circuit chip, (B) each said template circuit including a multiplicity of controlled current sources each with a zero-one selectable control and a selectable fixed value current level control, said multiplicity of controlled current sources including: (1) a voltage input from a reference, (2) a high gain differential amplifier with a plurality of inputs, (3) means for connecting a predetermined portion of said voltage input from a reference to a first of said inputs, (4) a block of parallel connected transistors on said chip, (5) a plurality of other transistors on said chip each having characteristics in common with each of said parallel connected transistors of said block, (6) means for connecting the output of said amplifier to all the gates of said transistors of said block, (7) a first resistor on said chip connected to conduct the combined current output of all said transistors of said block to ground, (8) means for connecting the voltage at the ungrounded end of said first resistor to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, and (9) means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones of said other transistors thereby causing the current produced by each of said other transistors to be equal to that of one of said transistors of said block or otherwise to be zero; and wherein said summer includes (10) a second resistor on said chip having a resistance with a known ratio to the resistance of said first resistor, (11) means for connecting the output currents of all said other transistors to pass through said second resistor to ground, and (12) means for accessing the voltage at the ungrounded end of said second resistor. (C) means for providing signals to select the status of said zero-one selectable control gates and said selectable fixed value current level controls. (D) means for supplying each one of said multiplicity of digital inputs to the control gate of a corresponding one of said multiplicity of controlled current sources in all of said template circuits. (E) each said template circuit further including a summer for algebraically summing the total current of all said controlled current sources of said template circuit. (F) each said template circuit further including means for detecting when an algebraic sum of current flows exceeds an established value at a respective summer of (E), and for producing a digital signal in response thereto. (G) means for registering the first N of said digital signals in the time sequence of said digital signals of (F) where N is at least one, and (H) means for generating a digital signal identifying at least the first one of said template circuits to have produced a digital signal of (F).
Claim 2
Dependent Claim
519 words
In a hybrid digital-analog computer parallel processor having a multiplicity of digital inputs the improvement comprising: (A) a plurality of template circuits, all the circuit elements of at least one complete template circuit being on a single integrated circuit chip, (B) each said template circuit including a multiplicity of controlled current sources each with a zero-one selectable control and a selectable fixed value current level control, said multiplicity of controlled current sources including: (1) a voltage input from a reference, (2) a high gain differential amplifier with a plurality of inputs, (3) means for connecting a predetermined portion of said voltage input from a reference to a first of said inputs, (4) a block of parallel connected transistors on said chip, (5) a plurality of other transistors on said chip each having characteristics in common with each of said parallel connected transistors of said block, (6) means for connecting the output of said amplifier to all the gates of said transistors of said block, (7) a first resistor on said chip connected to conduct the combined current output of all said transistors of said block to ground, (8) means for connecting the voltage at the ungrounded end of said first resistor to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, and (9) means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones of said other transistors thereby causing the current produced by each of said other transistors to be equal to that of one of said transistors of said block or otherwise to be zero; and wherein said summer includes (10) a second resistor on said chip having a resistance with a known ratio to the resistance of said first resistor, (11) means for connecting the output currents of all said other transistors to pass through said second resistor to ground, and (12) means for accessing the voltage at the ungrounded end of said second resistor. (C) means for providing signals to select the status of said zero-one selectable control gates and said selectable fixed value current level controls. (D) means for supplying each one of said multiplicity of digital inputs to the control gate of a corresponding one of said multiplicity of controlled current sources in all of said template circuits. (E) each said template circuit further including a summer for algebraically summing the total current of all said controlled current sources of said template circuit. (F) each said template circuit further including means for detecting when an algebraic sum of current flows exceeds an established value at a respective summer of (E), and for producing a digital signal in response thereto. (G) means for registering the first N of said digital signals in the time sequence of said digital signals of (F) where N is at least one, and (H) means for generating a digital signal identifying at least the first one of said template circuits to have produced a digital signal of (F).
Claim 3
Dependent Claim
258 words
An analog computation current-summing integrated circuit chip implemented with circuit elements of unkown parameter values, comprising: a high gain differential amplifier with a plurality of inputs, means for connecting a reference input voltage to a first of said inputs, a block of parallel connected transistors on said chip, a multiplicity of other transistors on said chip each having characteristics in common with each one of said parallel connected transistors of said block, means for connecting the output of said amplifier to gates of said transistors of said block, a first circuit element on said chip connected to receive the combined current output of all said transistors of said block, means for connecting the voltage of said first circuit element to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones or groups of said other transistors thereby causing the current produced by each of said other transistors to be equivalent to that of one of said transistors of said block or otherwise to be zero, a second circuit element on said chip having a parameter value with a known ratio to the parameter value of said first circuit element, means for connecting said second circuit element to receive the output currents of all said other transistors, and means for accessing the voltage at said second circuit element.
Claim 4
Dependent Claim
258 words
An analog computation current-summing integrated circuit chip implemented with circuit elements of unkown parameter values, comprising: a high gain differential amplifier with a plurality of inputs, means for connecting a reference input voltage to a first of said inputs, a block of parallel connected transistors on said chip, a multiplicity of other transistors on said chip each having characteristics in common with each one of said parallel connected transistors of said block, means for connecting the output of said amplifier to gates of said transistors of said block, a first circuit element on said chip connected to receive the combined current output of all said transistors of said block, means for connecting the voltage of said first circuit element to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones or groups of said other transistors thereby causing the current produced by each of said other transistors to be equivalent to that of one of said transistors of said block or otherwise to be zero, a second circuit element on said chip having a parameter value with a known ratio to the parameter value of said first circuit element, means for connecting said second circuit element to receive the output currents of all said other transistors, and means for accessing the voltage at said second circuit element.
Claim 5
Dependent Claim
29 words
Apparatus as recited in claim 2 further including a plurality of CMOS gating transistors for selecting certain of said other transistors to receive a gate voltage from said amplifier.
Claim 6
Dependent Claim
272 words
An analog computation current-summing integrated circuit chip implemented with circuit elements of unknown parameter values, comprising: a voltage input from a reference, a high gain differential amplifier with a plurality of inputs, means for connecting a predetermined portion of said reference input voltage to a first of said inputs, a block of parallel connected transistors on said chip, a multiplicity of other transistors on said chip each having characteristics in common with each of said parallel connected transistors of said block, means for connecting the output of said amplifier to all the gates of said transistors of said block, a first resistor on said chip connected to conduct the combined current output of all said transistors of said block to ground, means for connecting the voltage at the ungrounded end of said first resistor to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones of said other transistors thereby causing the current produced by each of said other transistors to be equal to that of one of said transistors of said block or otherwise to be zero, a second resistor on said chip having a resistance with a known ratio to the resistance of said first resistor, means for connecting the output currents of all said other transistors to pass through said second resistor to ground, and means for accessing the voltage at the ungrounded end of said second resistor.
Claim 7
Dependent Claim
272 words
An analog computation current-summing integrated circuit chip implemented with circuit elements of unknown parameter values, comprising: a voltage input from a reference, a high gain differential amplifier with a plurality of inputs, means for connecting a predetermined portion of said reference input voltage to a first of said inputs, a block of parallel connected transistors on said chip, a multiplicity of other transistors on said chip each having characteristics in common with each of said parallel connected transistors of said block, means for connecting the output of said amplifier to all the gates of said transistors of said block, a first resistor on said chip connected to conduct the combined current output of all said transistors of said block to ground, means for connecting the voltage at the ungrounded end of said first resistor to a second of said inputs of said amplifier in a sense to cause variations in output of said amplifier applied to said gates to cause the difference of its inputs to approach zero, means for applying a gate voltage substantially equal to the output voltage of said amplifier to selected ones of said other transistors thereby causing the current produced by each of said other transistors to be equal to that of one of said transistors of said block or otherwise to be zero, a second resistor on said chip having a resistance with a known ratio to the resistance of said first resistor, means for connecting the output currents of all said other transistors to pass through said second resistor to ground, and means for accessing the voltage at the ungrounded end of said second resistor.
Claim 8
Dependent Claim
29 words
Apparatus as recited in claim 4 further including a plurality of CMOS gating transistors for selecting certain of said other transistors to receive a gate voltage from said amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |