US5136590A — Kernel testing interface and method for automatin…

Claim 1

Independent Claim 187 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, a memory, and data and address buses, comprising the steps of: electrically substituting an emulation memory for the memory of said UUT, placing an executable program including data and at least a plurality of load instructions into said emulation memory at locations corresponding to a boot memory starting at a reset address; commanding a reset of said microprocessor, executing said program, detecting on said address bus at least one bit pattern appearing in response to at least one of the addresses corresponding to one of said load instructions, detecting on said address bus at least one bit pattern appearing in response to at least one of the data corresponding to one of said load instructions, analyzing said at least one bit pattern appearing in response to said at least one address and said at least one bit pattern appearing in response to said at least one of the data, and verifying operability or determining a fault in said UUT kernel responsive to said analyzing step.

Claim 2

Independent Claim 187 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, a memory, and data and address buses, comprising the steps of: electrically substituting an emulation memory for the memory of said UUT, placing an executable program including data and at least a plurality of load instructions into said emulation memory at locations corresponding to a boot memory starting at a reset address; commanding a reset of said microprocessor, executing said program, detecting on said address bus at least one bit pattern appearing in response to at least one of the addresses corresponding to one of said load instructions, detecting on said address bus at least one bit pattern appearing in response to at least one of the data corresponding to one of said load instructions, analyzing said at least one bit pattern appearing in response to said at least one address and said at least one bit pattern appearing in response to said at least one of the data, and verifying operability or determining a fault in said UUT kernel responsive to said analyzing step.

Claim 3

Dependent Claim 16 words

The method of claim 1 including the further step of testing power application to said microprocessor.

Claim 4

Dependent Claim 26 words

The method of claim 1 including the further step of testing power application to said microprocessor when a fault is determined responsive to said analyzing step.

Claim 5

Dependent Claim 14 words

The method of claim 2 including the further step of testing the microprocessor clock.

Claim 6

Dependent Claim 24 words

The method of claim 3 including the further step of testing the microprocessor clock when a fault is determined responsive to said analyzing step.

Claim 7

Dependent Claim 30 words

The method of claim 4 including the further step of generating a reset overdrive pulse to said microprocessor and determining whether a corresponding signal appears on the microprocessor reset line.

Claim 8

Dependent Claim 39 words

The method of claim 5 including the further step of generating a reset overdrive pulse to said microprocessor and determining whether a corresponding signal appears on the microprocessor reset line when a fault is determined by said analyzing step.

Claim 9

Dependent Claim 34 words

The method of claim 6 including the further step of sensing the voltage on forcing lines of the microprocessor and reporting a fault if any are at a voltage corresponding to an active state.

Claim 10

Dependent Claim 43 words

The method of claim 7 including the further step of sensing the voltage on forcing lines of the microprocessor and reporting a fault if any are at a voltage corresponding to an active state when a fault is determined by said analyzing step.

Claim 11

Dependent Claim 22 words

The method of claim 8 including the further step of monitoring the microprocessor control lines and determining if the microprocessor is stopped.

Claim 12

Dependent Claim 31 words

The method of claim 9 including the further step of monitoring the microprocessor control lines and determining if the microprocessor is stopped when a fault is determined by said analyzing step.

Claim 13

Dependent Claim 33 words

The method of claim 10 including the further step of monitoring the boot memory chip select line to determine if a pulse is received thereon responsive to a reset command to said microprocessor.

Claim 14

Dependent Claim 42 words

The method of claim 11 including the further step of monitoring the boot memory chip select line to determine if a pulse is received thereon responsive to a reset command to said microprocessor when a fault is determined by said analyzing step.

Claim 15

Independent Claim 136 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of a.) electrically substituting an emulation memory for the memory of said UUT, b.) placing at least one load instruction into an emulation memory, c.) commanding a reset of the UUT microprocessor, d.) executing the load instruction to place a predetermined bit pattern on a portion of said address bus, e.) detecting a bit pattern on a portion of said address bus, f.) repeating steps b.)-e.) for each of a plurality of said bit patterns in said sequence of bit patterns, and g.) evaluating the bit pattern on the address bus to detect whether there is an error in the performance of said load instruction.

Claim 16

Independent Claim 136 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of a.) electrically substituting an emulation memory for the memory of said UUT, b.) placing at least one load instruction into an emulation memory, c.) commanding a reset of the UUT microprocessor, d.) executing the load instruction to place a predetermined bit pattern on a portion of said address bus, e.) detecting a bit pattern on a portion of said address bus, f.) repeating steps b.)-e.) for each of a plurality of said bit patterns in said sequence of bit patterns, and g.) evaluating the bit pattern on the address bus to detect whether there is an error in the performance of said load instruction.

Claim 17

Dependent Claim 35 words

The method according to claim 14 wherein connections are made manually to said portion of said address bus and wherein a prompt is issued to identify said portion prior to each repetition of step f.)

Claim 18

Dependent Claim 26 words

The method according to claim 15 including the further step of providing an audible indication of at least one parameter of the result of step g.)

Claim 19

Independent Claim 139 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of a.) electrically substituting an emulation memory for the memory of said UUT, b.) loading one of a sequence of bit patterns into a location of said emulation memory, c.) commanding a reset of the UUT microprocessor, d.) generating a sync signal responsive to the reset of the microprocessor, e.) detecting a bit pattern on at least a portion of the data bus in accordance with said sync pulse. f.) repeating steps b.)-e.) for each of a plurality of said bit patterns in said sequence of bit patterns, and g.) analyzing the sequence of bit patterns detected by said detecting step to determine defects in said data bus.

Claim 20

Independent Claim 139 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of a.) electrically substituting an emulation memory for the memory of said UUT, b.) loading one of a sequence of bit patterns into a location of said emulation memory, c.) commanding a reset of the UUT microprocessor, d.) generating a sync signal responsive to the reset of the microprocessor, e.) detecting a bit pattern on at least a portion of the data bus in accordance with said sync pulse. f.) repeating steps b.)-e.) for each of a plurality of said bit patterns in said sequence of bit patterns, and g.) analyzing the sequence of bit patterns detected by said detecting step to determine defects in said data bus.

Claim 21

Dependent Claim 35 words

The method according to claim 17 wherein connections are made manually to said portion of said data bus and wherein a prompt is issued to identify said portion prior to each repetition of step f.)

Claim 22

Dependent Claim 26 words

The method according to claim 18 including the further step of providing an audible indication of at least one parameter of the result of step g.)

Claim 23

Independent Claim 180 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing at least one load instruction including a predetermined bit pattern as immediate data into an emulation memory at the reset address, commanding a reset of the UUT microprocessor, executing the load instruction to place said predetermined bit pattern on a portion of said address bus, detecting a resulting bit pattern on said data bus, placing a program including the complement of said predetermined bit pattern as immediate data in said emulation memory at the reset address, executing said program to: place a complement of said predetermined bit pattern on a portion of said data bus, and complement said data in said microprocessor, detecting a further resulting bit pattern on said address bus, and analyzing each of said resulting bit pattern and said further resulting bit pattern and verifying or detecting a fault on said data bus.

Claim 24

Independent Claim 180 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing at least one load instruction including a predetermined bit pattern as immediate data into an emulation memory at the reset address, commanding a reset of the UUT microprocessor, executing the load instruction to place said predetermined bit pattern on a portion of said address bus, detecting a resulting bit pattern on said data bus, placing a program including the complement of said predetermined bit pattern as immediate data in said emulation memory at the reset address, executing said program to: place a complement of said predetermined bit pattern on a portion of said data bus, and complement said data in said microprocessor, detecting a further resulting bit pattern on said address bus, and analyzing each of said resulting bit pattern and said further resulting bit pattern and verifying or detecting a fault on said data bus.

Claim 25

Dependent Claim 47 words

The method of claim 20, including the further step of comparing said resulting pattern and said further resulting pattern, attributing a fault to a line of said address bus if the comparison is inexact and attributing a fault to said data bus if said comparison is exact.

Claim 26

Dependent Claim 48 words

The method of claim 20, including the further step of analyzing the low order bits of each of the addresses accessed by said microprocessor executing said program, attributing a fault to said data bus if no fault is found in the low order lines of said address bus.

Claim 27

Dependent Claim 28 words

The method of claim 22 wherein full functionality of said data bus of said UUT is verified if no fault is found by either of said analyzing steps.

Claim 28

Independent Claim 128 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing at least one bit pattern into an emulation memory at at least a boot location and at another location within the bootspace memory, commanding reset of said microprocessor a plurality of times, generating a sync pulse in response to said step of commanding reset of said microprocessor, analyzing, in order, the voltage levels on power supply pins, clock pins, forcing pins and status pins of said microprocessor which appear upon successive ones of said commands for reset of said microprocessor to determine microprocessor functionality.

Claim 29

Independent Claim 128 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing at least one bit pattern into an emulation memory at at least a boot location and at another location within the bootspace memory, commanding reset of said microprocessor a plurality of times, generating a sync pulse in response to said step of commanding reset of said microprocessor, analyzing, in order, the voltage levels on power supply pins, clock pins, forcing pins and status pins of said microprocessor which appear upon successive ones of said commands for reset of said microprocessor to determine microprocessor functionality.

Claim 30

Independent Claim 118 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing a predetermined bit pattern as immediate data at a boot location of said emulation memory, commanding reset of said microprocessor, monitoring said address bus for detecting the appearance of all addresses appearing thereon, counting the number of addresses which are monitored between the appearance of the boot location and the appearance of said predetermined bit pattern, and developing a sync signal responsive to subsequent resets in accordance with the result of said counting step.

Claim 31

Independent Claim 118 words

A method of testing a kernel of a unit under test (UUT) by memory device emulation (MDE), said UUT having a microprocessor, memory and data and address buses comprising the steps of electrically substituting an emulation memory for the memory of said UUT, placing a predetermined bit pattern as immediate data at a boot location of said emulation memory, commanding reset of said microprocessor, monitoring said address bus for detecting the appearance of all addresses appearing thereon, counting the number of addresses which are monitored between the appearance of the boot location and the appearance of said predetermined bit pattern, and developing a sync signal responsive to subsequent resets in accordance with the result of said counting step.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-08-04	1996-02-03	1996-08-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-08-04	2000-02-03	2000-08-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-08-04	2004-02-03	2004-08-04	$7700.00	Window Closed / Lapsed

Kernel testing interface and method for automating diagnostics of microprocessor-based systems

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