Logic analyzer

Claim 1

A logic analyzer, characterized in that it has at least one acquisition module (24, 34) which can be connected to an associated target (21, 31) and which acquisition module comprises the following circuit arrangements: (a) clock selector means enabling the selection either of a constant-frequency internal clock signal or of an external clock signal derived from an associated target, selected clock signal appearing at the output of the sample clock signal; (b) sample register means to store data signals delivered by the target and sampled by the sample clock signal; (c) sample detector means which responds to the sample clock signal by delivering for each sampling as an output signal a sample signal from which the instant of time of sampling can be derived; (d) synchronizing circuit means comprising a synchronization register means for storing data signals read out of the sample register means in response to the sample clock signal and sampled by the internal clock signal, and logic circuit means responsive to the internal clock signal and to the sample signal for delivering sample marking pulses for marking sampling time; (e) event detector means for comparing data signals read out of the synchronization register means of the synchronization circuit means with a predetermined pattern and in the event of coincidence, for delivering an output signal corresponding to an event; (f) memory control means providing a logic link between control signals delivered by a trigger control means, one or more output signals of the event detector means and one or more sample marking pulses, for producing as output signal a recording marking pulse causing the storage of data signals which are read out of the synchronization register means in response to the internal timing signal and whose time position is marked by a corresponding sample marking pulse; and (g) data memory means controlled by the memory control means and operative to store data signals read out of the synchronization register means.