Activity masking with mask context of SIMD processors

Claim 2

A single instruction multiple data (SIMD) architecture including multiple interconnected processing elements, each of said processing elements comprising: memory means for storing data; function means for performing computational and/or Input/Output (I/O) operations; multi-operation instruction register means for storing an instruction for normally causing said function means to simultaneously perform multiple operations; mask register means for storing a plurality of mask bits, said mask register means including a mask context bit register holding a mask context bit, said mask context bit being logically combined with at least one of the plurality of mask bits for masking one of the operations; means for setting a condition mask bit, said condition mask bit being one of the plurality of mask bits, wherein the condition mask bit selectively prevents certain operations from being performed; and stack means for storing the contents of the mask register means during a subroutine call so as to save a context of the processing element during the subroutine call, wherein a state of the mask context bit prior to the subroutine call is stored in the stack means, and wherein a state of the condition mask bit is stored in the mask context bit register during the subroutine call, said stack means stacking multiple contents of the mask register means in sequence for multiple nested subroutine calls.

Claim 3

The SIMD architecture according to claim 1 wherein the mask context bit is selectively bit-wise logically ANDed with the at least one mask bit.

Claim 4

The SIMD architecture according to claim 2 wherein one bit of the mask register means is a hard-wired unconditional bit which overrides the mask context bit.

Claim 5

The SIMD architecture according to claim 1 wherein the mask register means includes a plurality of function unit bits.

Claim 6

The SIMD architecture according to claim 4 wherein one bit of the mask register means is a hard-wired true bit.

Claim 7

The SIMD architecture according to claim 4 wherein the mask register means includes eight bits selectively addressable by a three-bit address location.

Claim 8

The SIMD architecture according to claim 1 wherein a North-Western most processing element is selected to perform scalar operations.

Claim 9

The SIMD architecture according to claim 7 wherein the mask register means includes a scalar mask context bit, said scalar mask context bit being zero at every processing element except for the North-Western most processing element in order to perform scalar processing in the North-Western most processing element.

Claim 10

The SIMD architecture according to claim 1 further comprising return means for returning the contents of the stack means to the mask register means at the end of the subroutine call to put the mask register means back to its state prior to the subroutine call, and returning the mask context bit during the subroutine call to the condition mask bit before the subroutine call.

Claim 13

The method according to claim 10 wherein the step of selecting a mask bit from a mask bit register includes the steps of selecting a mask bit from a mask bit register including a hard-wired true bit.

Claim 14

The method according to claim 10 wherein the step of selecting a mask bit from a mask bit register includes the steps of selecting a mask bit from a mask bit register including a hard-wired unconditional bit which overrides the mask context bit.

Claim 15

The method according to claim 10 further comprising the step of logically ORing a bit in a global response flag register with a bit in a global response flag register from every other processing element to determine if any of the processing elements meet the conditional requirements of the conditional instruction.

Claim 16

The method according to claim 10 wherein the step of selecting a mask bit from a mask register includes selecting a mask bit from an eight bit function bit bank.

Claim 17

The method according to claim 10 further comprising the step of logically ANDing a special purpose mask context bit with a scalar mask context bit, wherein the scalar mask context bit can only be true at one PE in order to facilitate scalar processing.

Claim 18

The method according to claim 10 further comprising the step of returning the contents of the stack that was previously stored in the mask bit registers prior to the subroutine call to the mask bit registers after completion of the subroutine call.

Claim 19

A single instruction multiple data architecture including multiple interconnected processing elements, each of said processing elements comprising: memory means for storing data; function means for performing computational operations and Input/Output (I/O) operations; multi-operation instruction register means for storing an instruction for normally causing said function means to simultaneously perform their respective operations; mask register means for storing a plurality of mask bits, at least one mask bit being associated with the function means, said mask register means further including a mask context bit register for storing a mask context bit, said mask context bit being selectively bit-wise logically ANDed with at least one function mask bit; means for setting the at least one mask bit as a function of a condition of the data in said memory means, wherein the contents of said mask register means selectively prevents certain operations from being performed; stack means for storing the contents of the mask register means during a subroutine call so as to save a context of the processing element when the processing element performs a subroutine, wherein a state of the mask context bit prior to the subroutine call is stored in the stack means, and wherein the at least one function mask bit is stored in the mask context bit register during the subroutine call, said stack means stacking multiple contents of the mask register means in sequence for multiple nested subroutine calls; and return means for returning contents of the stack to the mask register means at an end of the subroutine call to put the mask register means back to its state before the subroutine call, said return means returning the state of the mask context bit register to the at least one function mask bit at the end of the subroutine call.

Claim 20

A single instruction multiple data architecture including multiple interconnected processing elements, each of said processing elements comprising: memory means for storing data; function means for performing computational operations and Input/Output (I/O) operations; multi-operation instruction register means for storing an instruction for normally causing said function means to simultaneously perform their respective operations; mask register means for storing a plurality of mask bits, at least one mask bit being associated with the function means, said mask register means further including a mask context bit register for storing a mask context bit, said mask context bit being selectively bit-wise logically ANDed with at least one function mask bit; means for setting the at least one mask bit as a function of a condition of the data in said memory means, wherein the contents of said mask register means selectively prevents certain operations from being performed; stack means for storing the contents of the mask register means during a subroutine call so as to save a context of the processing element when the processing element performs a subroutine, wherein a state of the mask context bit prior to the subroutine call is stored in the stack means, and wherein the at least one function mask bit is stored in the mask context bit register during the subroutine call, said stack means stacking multiple contents of the mask register means in sequence for multiple nested subroutine calls; and return means for returning contents of the stack to the mask register means at an end of the subroutine call to put the mask register means back to its state before the subroutine call, said return means returning the state of the mask context bit register to the at least one function mask bit at the end of the subroutine call.

Claim 21

The architecture according to claim 17 wherein one bit of a both the mask bits associated with the function means is a hard-wired true bit.

Claim 22

The architecture according to claim 17 wherein one bit of the mask register means is a hard-wired unconditional bit which overrides the mask context bit.

Claim 23

The architecture according to claim 17 wherein the mask register means includes a global response flag register for storing a global response flag bit, said global response flag bit being logically ORed with another global response flag bit of each processing element to determine if any of the processing elements meets conditional requirements of a particular instruction sequence.

Claim 24

The architecture according to claim 17 wherein the mask register means includes a scalar mask contect bit register storing a scalar mask context bit wherein the scalar mask context bit is zero everywhere except a North-Western most processing element in order to facilitate scalar processing.