Cellular array processor with individual cell-level data-dependent cell control and multiport input memory

Claim 2

In a processor array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port, first register means coupled to said output port of said ALU for determining the status of said cell and for providing status data, second register means coupled to said first register means and said controller and operative to receive instructions from said controller and status data from said first register means to store therein a code indicative of an operating condition for said cell said operating condition being selected from an active condition and an idle condition for said cell, whereby said cell has the ability to operate or remain idle depending upon the status data from the first register means and instructions received from said controller.

Claim 3

The processor array according to claim 1, wherein said processor array is arranged as a single instruction multiple data array.

Claim 4

The processor array according to claim 1, wherein said memory means is a RAM having a read address input, a read/write address input, with at least two outputs.

Claim 5

The processor array according to claim 1, wherein said first register means includes a status register for storing therein the result of an arithmetic operation implemented by said ALU comprising carry, negative, zero and overflow.

Claim 6

In a processor array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port, register means coupled to said output port of said ALU for determining the status of said cell, a control register coupled to said register means and said controller and operative to receive data and instruction from said controller and said register means to store therein as first code indicative of an operating condition for said cell and a second code indicative of an idle condition for said cell, said control register having a first input designated as a POP input for shifting to the right a received binary number and a second input designated as a PUSH input for shifting to the left a test condition result, whereby said cell has the ability to operate or remain idle depending on said data and instructions received.

Claim 7

In a processor array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port, register means coupled to said output port of said ALU for determining the status of said cell, a control register coupled to said register means and said controller and operative to receive data and instruction from said controller and said register means to store therein as first code indicative of an operating condition for said cell and a second code indicative of an idle condition for said cell, said control register having a first input designated as a POP input for shifting to the right a received binary number and a second input designated as a PUSH input for shifting to the left a test condition result, whereby said cell has the ability to operate or remain idle depending on said data and instructions received.

Claim 8

The processor array according to claim 5, wherein said control register is a clocked shift left, shift right, parallel in/parallel out shift register operative to shift to the right for a high on said POP input and operative to shift to the left for a high on said PUSH input.

Claim 9

The processor array according to claim 6, wherein said control register further has a third input designated as a left serial input for receiving data from said controller for shifting to the right and a fourth input designated as a right serial input for receiving data from said controller for shifting to the left.

Claim 10

The processor array according to claim 7, wherein said control register further includes a parallel input designated as LOAD for restoring the state of said register as controlled by said controller.

Claim 11

The processor array according to claim 7, wherein said controller further includes means for counting the number of bits PUSHED into said control register to determine whether said number of bits are capable of being accommodated by said register.

Claim 12

In a processor array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports; an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port; first register means coupled to said output port of said ALU for determining the status of said cell and for providing status data; second register means coupled to said first register means and said controller and operative to receive instructions from said controller and status data from said first register means to store therein a code indicative of an operating condition for said cell, said operating condition being selected from an active condition and an idle condition for said cell, whereby said cell has the ability to operate or remain idle depending upon the status data from the first register means and instructions received from said controller; and an array memory having stored therein a number of masks, said number corresponding to the sum of the square of the number of processing cells in a row and the square of the number of processing cells in a column of said array, said controller being operative to select any desired one of said masks by transmitting an address to said saddress generator, whereby any desired cells may be accessed through the selection of the proper mask.

Claim 13

In a processor array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports; an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port; first register means coupled to said output port of said ALU for determining the status of said cell and for providing status data; second register means coupled to said first register means and said controller and operative to receive instructions from said controller and status data from said first register means to store therein a code indicative of an operating condition for said cell, said operating condition being selected from an active condition and an idle condition for said cell, whereby said cell has the ability to operate or remain idle depending upon the status data from the first register means and instructions received from said controller; and an array memory having stored therein a number of masks, said number corresponding to the sum of the square of the number of processing cells in a row and the square of the number of processing cells in a column of said array, said controller being operative to select any desired one of said masks by transmitting an address to said saddress generator, whereby any desired cells may be accessed through the selection of the proper mask.

Claim 14

The processor array according to claim 10, wherein said masks include a first plurality of masks indicative of vertical columns M in said array and a second plurality of masks indicative of horizontal rows N in said array.

Claim 15

The processor array according to claim 9, wherein said program control memory comprises a plurality of random access memories (RAMS), with said controller being a programmed sequencer.

Claim 16

In a processing array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports; an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port; first register means coupled to said output port of said ALU for determining the status of said cell and for providing status data, said first register means including a status register for storing therein the result of an arithmetic operation implemented by said ALU comprising carry, negative zero and overflow; second register means coupled to said first register means and said controller and operative to receive instructions from said controller and status data from said first register means to store therein a code indicative of an operating condition for said cell, said operating condition being selected from an active condition and an idle condition for said cell, whereby said cell has the ability to operate or remain idle depending upon the status data from the first register means and instructions received from said controller; and a programmable logic array for decoding the status of the status data from said status register, the selected state being chosen by the controller with an output coupled to said second register.

Claim 17

In a processing array of the type including a plurality of individual processing cells arranged in a N×M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, the combination therewith of a processing cell structure for inclusion in said array said processing cell comprising: memory means having multiple input ports each for receiving separate input data from said controller and a plurality of output ports; an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of said memory means, with said arithmetic logic unit having an output port; first register means coupled to said output port of said ALU for determining the status of said cell and for providing status data, said first register means including a status register for storing therein the result of an arithmetic operation implemented by said ALU comprising carry, negative zero and overflow; second register means coupled to said first register means and said controller and operative to receive instructions from said controller and status data from said first register means to store therein a code indicative of an operating condition for said cell, said operating condition being selected from an active condition and an idle condition for said cell, whereby said cell has the ability to operate or remain idle depending upon the status data from the first register means and instructions received from said controller; and a programmable logic array for decoding the status of the status data from said status register, the selected state being chosen by the controller with an output coupled to said second register.