EP0035647A2
Expired / Lapsed
EP
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A SIMD data processing system
Assignee: International Business Machines Corp
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Filing: 1981-02-05
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Granted: —
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Expires: 2001-02-05
Abstract
Abstract This invention relates to a data processing system including an array of parallel processors (81) and a control unit (41). The system is of the type including addressable memory for registration of processing and machine status, as well as conditions in which at least some of the modular blocks in the instruction stream have been priority ordered. The system uses activity masks to register and control the execution status of each one of the processors in the parallel array. The system further includes, a set of instruction pointer registers, a set of order registers (153), a set of bit registers (155) indicative of active processors, and a set of condition bit registers (157). The instruction stream is preprocessed by selectively inserting instructions from the set consisting of ELSE X, JOIN X, and DATUM X at the beginning of predetermined ones of the blocks. This renders enforceable the priority ordering in the execution of the blocks. Upon the occurrence of an inactive processor the modular block, of an order less than the order of the block currently being executed, is pointed and the activity mask is altered so as to cause control to move to the block of lower order.
Inventors
- 👤 Hovey Raymond Strong, Jr.
- 👤 Raymond Amand Lorie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 21:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F9/30003; G06F9/3005; G06F9/30058; G06F9/3836; G06F9/3842; G06F9/3887
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
224 words
A data processing system, characterised in that the system includes an array of parallel processors (81) whose active or inactive execution status is regulated by an activity mask, a control unit (41) for interpreting instructions for scheduling basic block execution and for selectively executing instructions within the blocks on parallel processors in the array, each array processor (15) including a condition bit register (157) coupling the control unit and adapted to be set into a first or second value by a currently executing basic block at the control unit, an activity bit register (155) responsive to the condition bit register contents and adapted to be masked on for the first value and off for the second, an order register (153) also coupling the control unit and updated together with the argument of the first instruction of a basic block to be prospectively executed if the activity register is'masked off and the currently executed basic block if masked on, means for comparing the order register contents, upon the joint occurrence of one register of an inactive processor pointing to an order less than the order of a block currently being executed by an active processor and means including the comparing means for identifying the minimum value within the order registers and upon transfer of control and for masking the associated processor to the active state.
Claim 2
Dependent Claim
224 words
A data processing system, characterised in that the system includes an array of parallel processors (81) whose active or inactive execution status is regulated by an activity mask, a control unit (41) for interpreting instructions for scheduling basic block execution and for selectively executing instructions within the blocks on parallel processors in the array, each array processor (15) including a condition bit register (157) coupling the control unit and adapted to be set into a first or second value by a currently executing basic block at the control unit, an activity bit register (155) responsive to the condition bit register contents and adapted to be masked on for the first value and off for the second, an order register (153) also coupling the control unit and updated together with the argument of the first instruction of a basic block to be prospectively executed if the activity register is'masked off and the currently executed basic block if masked on, means for comparing the order register contents, upon the joint occurrence of one register of an inactive processor pointing to an order less than the order of a block currently being executed by an active processor and means including the comparing means for identifying the minimum value within the order registers and upon transfer of control and for masking the associated processor to the active state.
Claim 3
Dependent Claim
94 words
A system according to claim 1, in which the instruction stream is processed by selectively inserting instructions from a set consisting of ELSE, JOIN, and DATUM at the beginning of predetermined ones of the basic blocks so as to enforce the priority ordering in the execution of said blocks, and upon the occurrence of an inactive processor a basic block, which has an order less than the order of the basic block currently being executed, is pointed, the activity mask is selectively altered and control is moved to the basic block of lower order.
Claim 4
Dependent Claim
104 words
A system according to claim 2, in which the instruction stream is processed by inserting a JOIN instruction at the beginning of each target block of a left branch, inserting an ELSE instruction at the beginning of the target basic block of any right branch for which the corresponding left branch target basic block has a lower order, and inserting an ELSE instruction at the beginning of the target node of which each edge [i,j] satisfies the conditions that the interval (i,j) contains a JOIN or ELSE and either the edge [i,j] is not a left branch or the interval is incomplete and unprotected.
Claim 5
Dependent Claim
36 words
A system according to claim 2 or 3, in which the activity mask is altered and control is moved by executing one of the instructions from the set consisting of ELSE, JOIN, and BC (conditional branch).
Claim 6
Dependent Claim
74 words
A system according to claim 4, in which the ELSE instruction is executed by changing the order number of active processors of the array to be equal to the argument of the ELSE instruction, updating the instruction pointers for each active processor to the next instruction, while maintaining the instruction pointers for the inactive processors the same, and activating exactly those processors with the minimum order number by selectively altering the counterpart activity mask.
Claim 7
Dependent Claim
117 words
A system according to claim 1, in which M out of N processors are active, N - M processors being masked off as inactive while awaiting another program segment, each segment being labelled with a unique identifier, the segment label from the instruction is fetched and the minimum label number k is determined in the set of all N segments waiting execution by both the active and inactive processors, and all processors seeking to execute segment k being unmasked and the remaining processors being masked, this step being taken in over-lap relation such that at the end of the execution of segments k, another mask and branch operation (ELSE) will be executed and the next segment ascertained.
References Cited (Backward Citations)
No citation records indexed.
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