US5809293A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for program execution tracing within an integrated processor
Assignee: International Business Machines Corp
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Filing: 1994-07-29
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Granted: 1998-09-15
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Expires: 2014-07-29
Abstract
Abstract A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.
Inventors
- 👤 Jeffrey Todd Bridges
- 👤 Thomas K. Collopy
- 👤 James N. Dieffenderfer
- 👤 Thomas Joseph Irene
- 👤 Harry I. Linzer
- 👤 Thomas Andrew Sartorius
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466; G06F11/3648; G06F2201/00; G06F2201/865
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
60 words
A circuit for tracing real-time program execution within an integrated processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said circuit comprising: means for continuously monitoring branch target information during a normal operational mode within said processor; and means for providing said branch target information externally from said processor.
Claim 2
Dependent Claim
60 words
A circuit for tracing real-time program execution within an integrated processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said circuit comprising: means for continuously monitoring branch target information during a normal operational mode within said processor; and means for providing said branch target information externally from said processor.
Claim 3
Dependent Claim
34 words
The circuit as recited in claim 1 wherein said circuit and said processor reside coextensively within a packaged chip, said circuit further comprising: means for providing said branch target information externally from said chip.
Claim 4
Dependent Claim
21 words
The circuit as recited in claim 2 wherein said monitoring means is coupled to one or more registers within said processor.
Claim 5
Dependent Claim
25 words
The circuit as recited in claim 3 wherein said one or more registers includes a link register, a count register, and an instruction address register.
Claim 6
Dependent Claim
76 words
The circuit as recited in claim 2 wherein said providing means further comprises: a FIFO coupled to said monitoring means for temporarily storing said branch target information monitored with said processor; and serial logic circuitry, coupled to said FIFO and to one or more external pins of said chip, for serializing said branch target information obtained from said FIFO, said serial logic circuitry providing said serialized branch target information to said one or more external pins.
Claim 7
Dependent Claim
34 words
The circuit as recited in claim 2, further comprising: means for monitoring processor execution status; means for encoding said monitored status; and means for providing said encoded and monitored status externally from said chip.
Claim 8
Dependent Claim
19 words
The circuit as recited in claim 6 wherein said monitoring means comprises control logic circuitry embedded within said processor.
Claim 9
Dependent Claim
30 words
The circuit as recited in claim 6 wherein said processor status includes: instruction execution within said processor; exception occurrence within said program code; and branch execution within said program code.
Claim 10
Dependent Claim
22 words
The circuit as recited in claim 2, further comprising: means for initiating said tracing of said program execution within said integrated processor.
Claim 11
Dependent Claim
39 words
The circuit as recited in claim 9 wherein said initiating means further comprises: means for receiving an external signal operable to initiate said tracing; and means, coupled to said receiving means, for detecting a particular event within said processor.
Claim 12
Dependent Claim
20 words
The circuit as recited in claim 10 wherein said detecting means transmits a trace initiating signal to said providing means.
Claim 13
Dependent Claim
40 words
The circuit as recited in claim 9, further comprising: one or more registers for monitoring said branch target information at initiation of said tracing; and means for providing the contents of said one or more registers externally from said chip.
Claim 14
Dependent Claim
19 words
The circuit as recited in claim 5, further comprising: means for stalling said processor when said FIFO becomes back-logged.
Claim 15
Independent Claim
59 words
A method for tracing real-time program execution within an integrated processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said method comprising the steps of: continuously monitoring branch target information during a normal operational mode within said processor; and providing said branch target information externally from said processor.
Claim 16
Independent Claim
59 words
A method for tracing real-time program execution within an integrated processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said method comprising the steps of: continuously monitoring branch target information during a normal operational mode within said processor; and providing said branch target information externally from said processor.
Claim 17
Dependent Claim
22 words
The method as recited in claim 14 wherein said branch target information is monitored from one or more registers within said processor.
Claim 18
Dependent Claim
25 words
The method as recited in claim 15 wherein said one or more registers includes a link register, a count register, and an instruction address register.
Claim 19
Dependent Claim
39 words
The method as recited in claim 14 wherein said providing step further comprises the steps of: temporarily storing said branch target information, monitored with said processor, in a FIFO; and serializing said branch target information obtained from said FIFO.
Claim 20
Dependent Claim
28 words
The method as recited in claim 14, further comprising the steps of: monitoring processor execution status; encoding said monitored status; and providing said encoded and monitored status externally.
Claim 21
Dependent Claim
23 words
The method as recited in claim 14, further comprising the step of: initiating said tracing of said program execution within said integrated processor.
Claim 22
Dependent Claim
33 words
The method as recited in claim 19 wherein said initiating step further comprises the steps of: receiving an external signal operable to initiate said tracing; and detecting a particular event within said processor.
Claim 23
Dependent Claim
20 words
The method as recited in claim 17, further comprising the step of: stalling said processor when said FIFO becomes back-logged.
Claim 24
Dependent Claim
53 words
An integrated circuit comprising: a processor; an embedded memory that provides a portion of a program code executed by said processor; means for continuously monitoring branch target information during a normal operational mode within said processor; and means, coupled to said monitoring means, for providing said branch target information externally from said processor.
Claim 25
Dependent Claim
53 words
An integrated circuit comprising: a processor; an embedded memory that provides a portion of a program code executed by said processor; means for continuously monitoring branch target information during a normal operational mode within said processor; and means, coupled to said monitoring means, for providing said branch target information externally from said processor.
Claim 26
Dependent Claim
30 words
The circuit as recited in claim 22 wherein said circuit resides within a packaged chip, said circuit further comprising: means for providing said branch target information externally from said chip.
Claim 27
Dependent Claim
21 words
The circuit as recited in claim 23 wherein said monitoring means is coupled to one or more registers within said processor.
Claim 28
Dependent Claim
25 words
The circuit as recited in claim 24 wherein said one or more registers includes a link register, a count register, and an instruction address register.
Claim 29
Dependent Claim
76 words
The circuit as recited in claim 23 wherein said providing means further comprises: a FIFO coupled to said monitoring means for temporarily storing said branch target information monitored with said processor; and serial logic circuitry, coupled to said FIFO and to one or more external pins of said chip, for serializing said branch target information obtained from said FIFO, said serial logic circuitry providing said serialized branch target information to said one or more external pins.
Claim 30
Dependent Claim
34 words
The circuit as recited in claim 23, further comprising: means for monitoring processor execution status; means for encoding said monitored status; and means for providing said encoded and monitored status externally from said chip.
Claim 31
Dependent Claim
37 words
The circuit as recited in claim 23 wherein said chip is coupled to a data processing system comprising: a memory coupled to said processor; input means coupled to said processor; and output means coupled to said processor.
Claim 32
Dependent Claim
103 words
A data processing system comprising: a memory means; an input means; a display means; an input/output control means coupled to said display means and said input means; a processor; a bus for coupling said memory means, said input/output control means and said processor; and a circuit for tracing real-time program execution within said processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said circuit comprising: means for continuously monitoring branch target information during a normal operational mode within said processor; and means for providing said branch target information externally from said processor.
Claim 33
Dependent Claim
103 words
A data processing system comprising: a memory means; an input means; a display means; an input/output control means coupled to said display means and said input means; a processor; a bus for coupling said memory means, said input/output control means and said processor; and a circuit for tracing real-time program execution within said processor, said processor including an embedded cache memory that provides a portion of a program code executed by said processor, said circuit comprising: means for continuously monitoring branch target information during a normal operational mode within said processor; and means for providing said branch target information externally from said processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |