EP0945805A1
Expired / Lapsed
EP
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A cache coherency mechanism
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1999-03-15
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Granted: —
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Expires: 2019-03-15
Abstract
Abstract A computer system has a plurality of processors each for executing a sequence of instructions and at least one of the processors having a cache memory associated therewith. A memory provides an address space of that processor where data items are stored for use by all of the processors. A behaviour store holds in association with the address of each item a cache behaviour identifying the cacheable behaviour of the item, the cacheable behaviours including a software coherent behaviour and an automatically coherent behaviour. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behaviour of the specified address of the item. A method of modifying the coherency status of a cache in this manner is also described.
Inventors
- 👤 Andrew Michael Jones
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:18
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0837
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
212 words
A computer system comprising a plurality of processors, each
comprising an execution unit for executing a sequence of
instructions and at least one of the processors having associated
there with a cache memory having a plurality of cache locations
for holding items for use by the processor; storage circuitry having addressable storage locations in
the memory address space of said at least one processor in which
items are stored for use by the processors; a behaviour store for holding in association with an address
of an item a cache behaviour identifying the cacheable behaviour
of the item, wherein the cacheable behaviours include a software
coherent behaviour and an automatically coherent behaviour and
wherein the instructions for execution by the execution unit
include cache coherency instructions which each specify an
operation to be executed on the contents of a cache location and
an address in the storage circuitry; each processor being operable responsive to the cache
coherency instructions to execute an operation on the contents
of the specified cache location and to effect a cache coherency
operation to render the contents coherent with the storage
circuitry in a manner dependent on the cacheable behaviour of the
specified address and whether or not the processor contains a
cache coherency unit for automatically implementing coherency.
Claim 2
Dependent Claim
44 words
A computer system according to claim 1, which comprises a
cache coherency unit for automatically implementing coherency and
wherein said cache coherency instructions effect a cache
coherency operation for automatically coherent and software
coherent behaviour dependent on the nature of the cache coherency
unit.
Claim 3
Dependent Claim
31 words
A computer system according to claim 1, which has no cache
coherency unit for automatically implementing coherency, wherein
items having an automatically coherent behaviour are denied
access to the cache memory.
Claim 4
Dependent Claim
20 words
A computer system according to any preceding claim, wherein
each of the processors has a respective cache memory associated
therewith.
Claim 5
Dependent Claim
22 words
A computer system according to any preceding claim, wherein
the storage circuitry comprises a main memory accessible by all
of the processors.
Claim 6
Dependent Claim
34 words
A computer system according to any preceding claim, wherein
each item in the or each cache memory is stored in association
with a valid bit which indicates whether or not that item is
valid.
Claim 7
Dependent Claim
41 words
A computer system according to any preceding claim, wherein
each item in the or each cache memory is stored in association
with a dirty bit which indicates whether or not that item has
been modified with respect to the storage circuitry.
Claim 8
Dependent Claim
24 words
A computer system according to any preceding claim, wherein
the cacheable behaviours include an unshared behaviour for items
unique to one of said processors.
Claim 9
Dependent Claim
26 words
A computer system according to any preceding claim, wherein
the cacheable behaviours include an uncacheable behaviour for
accesses to memory devices other than said storage circuitry.
Claim 10
Dependent Claim
36 words
A computer system according to any preceding claim, wherein
the cacheable behaviours include a device behaviour for accesses
to devices other than memory devices, said devices being
addressable in the memory address space of the processors.
Claim 11
Dependent Claim
37 words
A computer system according to any preceding claim, wherein
the cache coherency instructions include a flush instruction
which makes dirty items in the cache memory associated with said
at least one processor visible to the other processors.
Claim 12
Dependent Claim
24 words
A computer system according to any preceding claim, wherein
the cache coherency instructions include a purge instruction
which removes items from the cache memory.
Claim 13
Dependent Claim
49 words
A computer system according to any preceding claim, wherein
the cache coherency instructions include a coherent instruction
which makes dirty items in the cache memory associated with said
at least one processor visible to the other processors and
ensures that stale items are not read from the cache memory.
Claim 14
Dependent Claim
29 words
A computer system according to any preceding claim, wherein
the cache coherency instructions include a validate instruction
which ensures that stale items are not read from the cache
memory.
Claim 15
Independent Claim
211 words
A method of modifying the coherency status of the contents
of a cache in a computer system comprising a plurality of
processors each having an execution unit for executing a sequence
of instructions and at least one of the processors having
associated therewith a cache memory, and storage circuitry having
addressable storage locations in the memory address space of said
at least one processor in which items are stored for use by the
processors, the method comprising: defining for each item a cacheable behaviour of the item,
wherein the cacheable behaviours include a software coherent
behaviour and an automatically coherent behaviour; holding in a behaviour store in association with an address
for each item a cache behaviour identifying the cacheable
behaviour of the item; executing in the execution unit cache coherency instructions
which each specify an operation to be executed on the contents
of a cache location in the cache memory and an address in the
storage circuitry; executing an operation on the contents of the specified
cache location and effecting a cache coherency operation to
render the contents coherent with the storage circuitry in a
manner dependent on the cacheable behaviour of the specified
address and whether or not the processor contains a cache
coherency unit for automatically implementing coherency.
Claim 16
Dependent Claim
46 words
A method according to claim 15, wherein the computer system
comprises a cache coherency unit for automatically implementing
coherency and wherein said cache coherency instructions effect
a cache coherency operation for automatically coherent and
software coherent behaviour dependent on the nature of the cache
coherency unit.
Claim 17
Dependent Claim
33 words
A method according to claim 15, wherein the computer system
has no cache coherency unit for automatically implementing
coherency, wherein items having an automatically coherent
behaviour are denied access to the cache memory.
Claim 18
Dependent Claim
35 words
A method according to claim 15, 16 or 17, wherein each item
in the or each cache memory is stored in association with a valid
bit which indicates whether or not that item is valid.
Claim 19
Independent Claim
43 words
A method according to any of claims 15 to 18, wherein each
item in the or each cache memory is stored in association with
a dirty bit which indicates whether or not that item has been
modified with respect to the storage circuitry.
Claim 20
Independent Claim
26 words
A method according to any of claims 15 to 19, wherein the
cacheable behaviours include an unshared behaviour for items
unique to one of said processors.
Claim 21
Independent Claim
28 words
A method according to any of claims 15 to 20, wherein the
cacheable behaviours include an uncacheable behaviour for
accesses to memory devices other than said storage circuitry.
Claim 22
Independent Claim
38 words
A method according to any of claims 15 to 21, wherein the
cacheable behaviours include a device behaviour for accesses to
devices other than memory devices, said devices being addressable
in the memory address space of the processors.
Claim 23
Independent Claim
39 words
A method according to any of claims 15 to 22, wherein the
cache coherency instructions include a flush instruction which
makes dirty items in the cache memory associated with said at
least one processor visible to the other processors.
Claim 24
Independent Claim
26 words
A method according to any of claims 15 to 23, wherein the
cache coherency instructions include a purge instruction which
removes items from the cache memory.
Claim 25
Independent Claim
31 words
A method according to any of claims 15 to 24, wherein the
cache coherency instructions include a validate instruction which
ensures that stale items are not read from the cache memory.
References Cited (Backward Citations)
US5091846A
Cited
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