US5884023A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for testing an integrated circuit with user definable trace function
Assignee: Texas Instruments Inc
•
Filing: 1996-12-09
•
Granted: 1999-03-16
•
Expires: 2016-12-09
Abstract
Abstract A method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216. The digital processor then monitors the message passing register for a handshake signal from the test host processor. When a handshake signal is received, trace data is written into the message passing register by user definable code in a background manner and transferred to the test host processor.
Inventors
- 👤 Gary L. Swoboda
- 👤 Eric J. Stotzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2268; G06F11/30; G06F11/34; G06F11/3466; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
146 words
A method for testing a digital processor, said digital processor having a memory portion and a test port, comprising the steps of: defining an area of said memory portion as a trace region; executing an application program on said digital processor until a preselected event occurs; storing at least one data item in a location in said trace region in response to said preselected event by said digital processor executing a monitor program included with said application program, such that said digital processor continues to execute said application program after said data item is stored, wherein said monitor program is operable to perform additional processing and may be varied by loading a new application program; and transferring said data item to a test host processor through said test port such that said digital processor continues to execute said application program after said data item is transferred.
Claim 2
Independent Claim
146 words
A method for testing a digital processor, said digital processor having a memory portion and a test port, comprising the steps of: defining an area of said memory portion as a trace region; executing an application program on said digital processor until a preselected event occurs; storing at least one data item in a location in said trace region in response to said preselected event by said digital processor executing a monitor program included with said application program, such that said digital processor continues to execute said application program after said data item is stored, wherein said monitor program is operable to perform additional processing and may be varied by loading a new application program; and transferring said data item to a test host processor through said test port such that said digital processor continues to execute said application program after said data item is transferred.
Claim 3
Dependent Claim
50 words
The method of claim 1 wherein said digital processor further comprises a message passing register and wherein the step of transferring said data item further comprises moving said data item from said trace region to said message passing register by means of instructions executed under control of said digital processor.
Claim 4
Dependent Claim
39 words
The method of claim 1 the step of storing at least one data item further comprises: determining if said trace region is full; and sending a notification message to said test host processor if said trace region is full.
Claim 5
Dependent Claim
18 words
The method of claim 3 wherein the step of storing said data item is repeated at least once.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein said data item is a memory address.
Claim 7
Dependent Claim
14 words
The method of claim 1 wherein said data item is a program counter address.
Claim 8
Dependent Claim
13 words
The method of claim 1 wherein said data item is a register content.
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein said preselected event is an application program execution discontinuity.
Claim 10
Dependent Claim
13 words
The method of claim 1 wherein said preselected event is an address breakpoint.
Claim 11
Dependent Claim
19 words
The method of claim 1 further comprising inserting a means for specifying said preselected event in said application program.
Claim 12
Independent Claim
192 words
A method for testing a digital processor, said digital processor having a memory portion, a test port, and a message passing register, comprising the steps of: A. defining an area of said memory portion as a trace region; B. executing an application program on said digital processor until a preselected event occurs; C. storing at least one data item in a location in said trace region in response to said preselected event by said digital processor executing a monitor program included with said application program, such that said digital processor continues to execute said application program after said data item is stored, wherein said monitor program is operable to perform additional processing and may be varied by loading a new application program; D. repeating steps B-C until said trace region is full; and E. transferring at least one said data item to a test host processor through said test port by moving said data item from said trace region to said message passing register by means of instructions executed under control of said digital processor such that said digital processor continues to execute said application program after said data item is transferred.
Claim 13
Independent Claim
192 words
A method for testing a digital processor, said digital processor having a memory portion, a test port, and a message passing register, comprising the steps of: A. defining an area of said memory portion as a trace region; B. executing an application program on said digital processor until a preselected event occurs; C. storing at least one data item in a location in said trace region in response to said preselected event by said digital processor executing a monitor program included with said application program, such that said digital processor continues to execute said application program after said data item is stored, wherein said monitor program is operable to perform additional processing and may be varied by loading a new application program; D. repeating steps B-C until said trace region is full; and E. transferring at least one said data item to a test host processor through said test port by moving said data item from said trace region to said message passing register by means of instructions executed under control of said digital processor such that said digital processor continues to execute said application program after said data item is transferred.
Claim 14
Dependent Claim
76 words
The method of claim 11 wherein step F further comprises: sending a notification signal through said test port from said digital processor to said test host processor when at least one said data item is in said trace region; and waiting for a handshake signal through said test port from said test host processor to said digital processor to indicate that said test host processor is ready to accept said data item from said digital processor.
Claim 15
Dependent Claim
41 words
The method of claim 12, in which: the step of sending a notification signal further comprises setting a bit in said message register; and the step of waiting for a handshake signal further comprises monitoring a bit in said message register.
Claim 16
Independent Claim
243 words
A method for testing a digital processor, said digital processor having a memory portion, a test port, and a message passing register, comprising the steps of: A. defining an area of said memory portion as a trace region; B. executing an application program on said digital processor until a preselected event occurs; C. storing at least one data item in a location in said trace region in response to said preselected event, such that said digital processor continues to execute said application program after said data item is stored; D. repeating steps B-C until said trace region is full; E. sending a notification signal through said test port from said digital processor to said test host processor when at least one said data item is in said trace region by setting a bit in said message register; and F. waiting for a handshake signal through said test port from said test host processor to said digital processor by monitoring a bit in said message register to indicate that said test host processor is ready to accept said data item from said digital processor; and E. transferring at least one said data item to a test host processor through said test port by moving said data item from said trace region to said message passing register by means of instructions executed under control of said digital processor such that said digital processor continues to execute said application program after said data item is transferred.
Claim 17
Independent Claim
243 words
A method for testing a digital processor, said digital processor having a memory portion, a test port, and a message passing register, comprising the steps of: A. defining an area of said memory portion as a trace region; B. executing an application program on said digital processor until a preselected event occurs; C. storing at least one data item in a location in said trace region in response to said preselected event, such that said digital processor continues to execute said application program after said data item is stored; D. repeating steps B-C until said trace region is full; E. sending a notification signal through said test port from said digital processor to said test host processor when at least one said data item is in said trace region by setting a bit in said message register; and F. waiting for a handshake signal through said test port from said test host processor to said digital processor by monitoring a bit in said message register to indicate that said test host processor is ready to accept said data item from said digital processor; and E. transferring at least one said data item to a test host processor through said test port by moving said data item from said trace region to said message passing register by means of instructions executed under control of said digital processor such that said digital processor continues to execute said application program after said data item is transferred.
Claim 18
Dependent Claim
13 words
The method of claim 14 wherein said data item is a memory address.
Claim 19
Dependent Claim
14 words
The method of claim 14 wherein said data item is a program counter address.
Claim 20
Dependent Claim
13 words
The method of claim 14 wherein said data item is a register content.
Claim 21
Dependent Claim
15 words
The method of claim 14 wherein said preselected event is an application program execution discontinuity.
Claim 22
Dependent Claim
13 words
The method of claim 14 wherein said preselected event is an address breakpoint.
References Cited (Backward Citations)
JPS61233651A
Cited
US4701921A
Cited
US4872169A
Cited
US4912636A
Cited
US5329471A
Cited
US4860290A
Cited
US5535331A
Cited
US5263143A
Cited
US5084874A
Cited
US5072418A
Cited
JPH04345906A
Cited
US5425036A
Cited
US5621651A
Cited
US5566300A
Cited
US5809293A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |