Enhanced test circuit

Claim 2

A test circuit within an integrated circuit comprising: a test cell having an input for receiving data, an output for supplying data, an input for receiving test data, an output for supplying test data, and operable to selectively store one of said inputs to said cell; and compare circuitry within said test cell to compare said input for receiving data to a predefined value and generate a control signal indicative of whether said input matches said predefined value.

Claim 3

The test circuit of claim 1 wherein said test cell includes a memory for storing said predefined value.

Claim 4

The test circuit of claim 1 wherein said test circuit further comprises a plurality of test cells each with an associated comparator to compare an input to a predetermined value and generate a respective control signal indicative of whether said input matches said predefined value.

Claim 5

The test circuit of claim 3 and further comprising circuitry to determine whether all of said respective control signals indicates a match.

Claim 6

The test circuit of claim 4 and further comprising circuitry to force a match condition from one or more of said associated compare circuitries.

Claim 7

The test circuit of claim 1 wherein said compare circuitry comprises an exclusive OR gate.

Claim 8

The test circuit of claim 6 wherein said compare circuitry comprises a NAND gate having one input connected to the output of said exclusive OR gate and one input connected to a masking control signal, such that a signal indicating a match will be generated in response to a masking control signal of a predetermined value.

Claim 9

The test circuit within an integrated circuit comprising: a plurality of test cells each coupled to an input or output of the integrated circuit and having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, each having an output for transmitting test data to other test cells; and one or more of said test cells having signature analysis circuits operable to calculate a checksum on a stream of data input to the test circuit.

Claim 10

The test circuit within an integrated circuit comprising: a plurality of test cells each coupled to an input or output of the integrated circuit and having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, each having an output for transmitting test data to other test cells; and one or more of said test cells having signature analysis circuits operable to calculate a checksum on a stream of data input to the test circuit.

Claim 11

The test circuit of claim 8 and further comprising making circuitry coupled to said signature analysis circuits and responsive to a control input signal to mask unwanted signature analysis circuits from the checksum calculation.

Claim 12

The test circuit of claim 8 and further comprising control circuitry to disable the signature analysis circuitry.

Claim 13

The test circuit of claim 8 and further comprising programmable polynomial tap circuitry operable to receive a feedback input signal from adjacent test cells and operable to transmit a feedback output signal to adjacent cells and responsive to a control input signal to exclude ones of said signature analysis circuits from the checksum calculation.

Claim 14

The test circuit of claim 8 wherein said signature analysis circuitry comprises an exclusive OR gate having an output connected to the input of said test cell, a first input coupled to a input node at which said stream of data is input and a second input coupled to an output from a next test cell.

Claim 15

A test circuit within an integrated circuit comprising: a plurality of test cells operable to store respective inputs to a plurality thereto; said test cells also operable to input and output data for an integrated circuit and operable to input and output test data; and one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, each having an input for received pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.

Claim 16

A test circuit within an integrated circuit comprising: a plurality of test cells operable to store respective inputs to a plurality thereto; said test cells also operable to input and output data for an integrated circuit and operable to input and output test data; and one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, each having an input for received pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.

Claim 17

The test circuit of claim 13 wherein test cells include shift circuitry to shift data stored therein to a next pattern generation circuit.

Claim 18

The test circuit of claim 13 and further comprising control circuitry to disable said pattern generation circuits.

Claim 19

The test circuit of claim 13 and further comprising programmable polynomial tap circuitry to exclude ones of said pattern generation circuits from the pattern generation.

Claim 20

Test circuitry on-board an integrated circuit, comprising: input and output buffer circuitry for receiving and transmitting user defined data and control signals; and test circuits coupled to said input and output buffer circuitry made up of a plurality of test cells operable to store respective inputs to a plurality thereto; each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to other test cells.

Claim 21

Test circuitry on-board an integrated circuit, comprising: input and output buffer circuitry for receiving and transmitting user defined data and control signals; and test circuits coupled to said input and output buffer circuitry made up of a plurality of test cells operable to store respective inputs to a plurality thereto; each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to other test cells.

Claim 22

The integrated circuit of claim 17 wherein one or more of the said test cells contains signature analysis circuits operable to calculate a checksum on the stream of data input to the test circuit.

Claim 23

The integrated circuit of claim 18 wherein one or more of said test cells further comprises programmable polynomial tap circuitry operable to receive a feedback input signal from adjacent test cells and operable to transmit a feedback output signal to adjacent cells and responsive to a control input signal to exclude ones of said signature analysis circuits from the checksum calculation.

Claim 24

The integrated circuit of claim 18 wherein one or more of said test cells containing said signature analysis circuits further comprises masking circuitry responsive to a control signal operable to mask unwanted ones of said signature analysis circuits from said checksum calculation.

Claim 25

Test circuitry on-board an integrated circuit, comprising: input and output buffer circuitry operable to receive and transmit user defined data and control signals; test circuitry coupled to said input and output circuitry and comprised of a plurality of test cells operable to store respective inputs thereto; each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to the other test cells; and one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, having an input for receiving pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.

Claim 26

Test circuitry on-board an integrated circuit, comprising: input and output buffer circuitry operable to receive and transmit user defined data and control signals; test circuitry coupled to said input and output circuitry and comprised of a plurality of test cells operable to store respective inputs thereto; each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to the other test cells; and one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, having an input for receiving pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.