US5996092A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for tracing program execution within a processor before and after a triggering event
Assignee: International Business Machines Corp
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Filing: 1996-12-05
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Granted: 1999-11-30
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Expires: 2016-12-05
Abstract
Abstract A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.
Inventors
- 👤 Victor Roberts Augsburg
- 👤 Jeffrey Todd Bridges
- 👤 Thomas K. Collopy
- 👤 James N. Dieffenderfer
- 👤 Thomas Andrew Sartorius
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
82 words
A method for tracing real-time program execution within a processor, said method comprising the steps of: periodically generating one or more synchronizing events occurring in said processor, wherein said one or more synchronizing events signify a state of said processor; detecting a triggering event occurring in said processor; tracing instructions occurring after said one or more synchronizing events and before and after said triggering event; and providing said one or more synchronizing events, triggering event, and traced instructions externally from said processor.
Claim 2
Independent Claim
82 words
A method for tracing real-time program execution within a processor, said method comprising the steps of: periodically generating one or more synchronizing events occurring in said processor, wherein said one or more synchronizing events signify a state of said processor; detecting a triggering event occurring in said processor; tracing instructions occurring after said one or more synchronizing events and before and after said triggering event; and providing said one or more synchronizing events, triggering event, and traced instructions externally from said processor.
Claim 3
Dependent Claim
53 words
The method as recited in claim 1, further comprising the steps of: storing said one or more synchronizing events and said traced instructions in a FIFO; serializing said one or more synchronizing events and said traced instructions; and transmitting said serialized one or more synchronizing events and traced instructions to a trace tool.
Claim 4
Dependent Claim
43 words
Thee method as recited in claim 2, wherein said step of periodically generating one or more synchronizing events further comprises the step of: copying contents of one or more registers embedded within said processor to said FIFO in response to a counter value.
Claim 5
Dependent Claim
85 words
A circuit for tracing real-time program execution within a processor comprising: circuitry for periodically generating one or more synchronizing events occurring in said processor wherein said one or more synchronizing events signify a state of said processor; circuitry for detecting a triggering event occurring in said processor; circuitry for tracing instructions occurring after said one or more synchronizing events and before and after said triggering event; and circuitry for providing said one or more synchronizing events, triggering event, and traced instructions externally from said processor.
Claim 6
Dependent Claim
85 words
A circuit for tracing real-time program execution within a processor comprising: circuitry for periodically generating one or more synchronizing events occurring in said processor wherein said one or more synchronizing events signify a state of said processor; circuitry for detecting a triggering event occurring in said processor; circuitry for tracing instructions occurring after said one or more synchronizing events and before and after said triggering event; and circuitry for providing said one or more synchronizing events, triggering event, and traced instructions externally from said processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |