US5675729A
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US
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Method and apparatus for performing on-chip measurement on a component
Assignee: Sun Microsystems Inc
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Filing: 1996-08-19
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Granted: 1997-10-07
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Expires: 2016-08-19
Abstract
Abstract The system of the present invention includes programmable logic to generate watchpoint traps which cause a branch to determined trap code and breakpoint signals which cause the stopping of the system dock. Furthermore, the system can measure system performance criteria. The logic is flexible and easy to program, but sophisticated in application to provide a variety of criteria that trigger on events which in turn increment the counters. In the preferred embodiment, the system includes two counters and trigger decode logic to increment the counters. Each counter is independently programmable to enable the user to determine such performance information as average latency, which is a combination of one counter counting the number of occurrences of a particular event and a second counter counting the duration of the events. Both counters can be programmed to measure on edges or levels of signals. In addition, the triggers can be used in a cascaded structure, wherein the first counter is used to generate a trigger which may be further qualified by the second counter. Using this implementation, a more flexible counting strategy is provided. Furthermore, by using the two counters in a cascaded fashion, the occurrence on one type of event can be used to monitor the occurrence of a second type of event in order to determine the occurrence of a combination of events. In addition, both watchpoint traps and breakpoint signals can be generated based upon the occurrence of a variety of events internal to the component and not easily accessible during execution by the user.
Inventors
- 👤 Peter Arnold Mehring
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3409; G06F11/3466; G06F11/348; G06F2201/00; G06F2201/86; G06F2201/88
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
129 words
In an integrated component located on a chip, said integrated component comprising a processor and an apparatus for detecting events which occur on the integrated component, said apparatus for detecting events comprising: trigger decode logic comprising; a plurality of inputs for receiving signals indicative of occurrences of events, and a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting a first output trigger signal when at least one event identified by the first event select register occurs; counter logic for counting a number of output trigger signals generated comprising; an input coupled to receive the first output trigger signal, and a count incrementor for selectively incrementing a first count for each first output trigger signal received.
Claim 2
Dependent Claim
129 words
In an integrated component located on a chip, said integrated component comprising a processor and an apparatus for detecting events which occur on the integrated component, said apparatus for detecting events comprising: trigger decode logic comprising; a plurality of inputs for receiving signals indicative of occurrences of events, and a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting a first output trigger signal when at least one event identified by the first event select register occurs; counter logic for counting a number of output trigger signals generated comprising; an input coupled to receive the first output trigger signal, and a count incrementor for selectively incrementing a first count for each first output trigger signal received.
Claim 3
Dependent Claim
31 words
The apparatus as set forth in claim 1, wherein said counter logic further comprises an output signal generator for generating an event signal when the first count reaches a predetermined value.
Claim 4
Dependent Claim
41 words
The apparatus as set forth in claim 2, wherein said count incrementor comprises a first counter register for storing a current first count and said output signal generator generates an event signal when the first count overflows the first counter register.
Claim 5
Dependent Claim
42 words
The apparatus as set forth in claim 3, wherein said counter logic further comprises a count load input for loading the first counter register with a predetermined count such that an event signal is generated when a programmed count of triggers occurs.
Claim 6
Dependent Claim
28 words
The apparatus as set forth in claim 2, wherein said counter logic is programmable such that an event signal is generated when a programmed count of triggers occurs.
Claim 7
Dependent Claim
30 words
The apparatus as set forth in claim 2, further comprising watchpoint trigger logic coupled to receive the event signal for generating a trap to the processor on an instruction boundary.
Claim 8
Dependent Claim
32 words
The apparatus as set forth in claim 2, further comprising breakpoint trigger logic coupled to receive the event signal for generating a breakpoint to stop the processor on a clock cycle boundary.
Claim 9
Dependent Claim
29 words
The apparatus as set forth in claim 2, further comprising scan logic for performing a scan of a state of the integrated component when the event signal is generated.
Claim 10
Dependent Claim
134 words
The apparatus as set forth in claim 1, wherein said count incrementor further comprises a first multiplexer which receives as a first input a current first count stored in a first counter register and as a second input the current first count incremented by one, and outputs a value selected by the first output trigger signal to be stored in the first counter register, such that if the first output trigger signal is in a first state indicative that an event occurred, the value output and stored in the first counter register is the current first count incremented by one, and if the first output trigger signal is in a second state indicative that an event has not occurred, the value output and stored in the first counter register is the current first count.
Claim 11
Dependent Claim
19 words
The apparatus as set forth in claim 9, wherein said first multiplexer generates an output value every clock cycle.
Claim 12
Dependent Claim
42 words
The apparatus as set forth in claim 1, the counter logic further comprising a count output from which the first count located in the counter logic are read, said processor further comprising logic to read the count output to gain performance information.
Claim 13
Dependent Claim
70 words
The apparatus as set forth in claim 1, wherein said trigger decode logic further comprises: a level detector for detecting duration of at least one event; an edge detector for detecting the occurrences of at least one event; and an edge/level select for selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event.
Claim 14
Dependent Claim
32 words
The apparatus as set forth in claim 12, wherein said first event select register further comprises a bit to be used by the edge/level select to select an edge or level detect.
Claim 15
Dependent Claim
99 words
The apparatus as set forth in claim 1, wherein said trigger decode logic further comprises: AND gate logic coupled to receive as input signals identifying each selected event that occurs, said AND gate logic performing a logical AND of the input signals to generate the first output trigger signal; OR gate logic coupled to receive as input signals identifying each selected event that occurs, said OR gate logic performing a logical OR of the input signals to generate the first output trigger signal; and a combinatorial logic selector for selecting the OR gate logic or the AND gate logic.
Claim 16
Dependent Claim
35 words
The apparatus as set forth in claim 14, wherein said first event select register further comprises a bit used by the combinatorial logic selector for selecting the OR gate logic or the AND gate logic.
Claim 17
Dependent Claim
77 words
The apparatus as set forth in claim 1, wherein said trigger decode logic further comprises a second event select register comprising data which identifies selectively events to generate a second trigger signal, said trigger decode logic outputting a second output trigger signal when at least one event identified by the second event select register occurs; said counter logic further comprising a second count incrementor for selectively incrementing a second count for each second output trigger signal received.
Claim 18
Dependent Claim
102 words
The apparatus as set forth in claim 16, wherein said trigger decode logic further comprises a second event select register comprising data which identifies selectively events to generate a second trigger signal, said trigger decode logic outputting a second output trigger signal when at least one event identified by the second event select register occurs; said counter logic further comprising a second count incrementor for selectively incrementing a second count for each second output trigger signal received; and said counter logic further comprising trigger combination logic for selectively generating the event signal when the first count and second count reach predetermined values.
Claim 19
Dependent Claim
47 words
The apparatus as set forth in claim 17, wherein: said trigger combination logic comprises providing an input event signal to the first trigger decode logic when the second count reaches a determined value; such that a cascaded count of events to generate the event signal is performed.
Claim 20
Dependent Claim
57 words
The apparatus as set forth in claim 18, further comprising logic to hold the input event signal indicative that the second count reached a determined value such that a first output trigger signal is generated for multiple clock cycles after an initial generation of the input event signal indicative that the second count reached a determined value.
Claim 21
Dependent Claim
31 words
The apparatus as set forth in claim 17, wherein said trigger combination logic comprises count selector for selecting the first count and second count to use to generate the event signal.
Claim 22
Dependent Claim
54 words
The apparatus as set forth in claim 16, wherein the counter logic further comprises a first and second count output from which the first and second count of events stored in the counter logic are read, said processor further comprising logic to read the first count and second count output to gain performance information.
Claim 23
Dependent Claim
22 words
The apparatus as set forth in claim 21, said processor combining the first count and second count to determine specific performance information.
Claim 24
Dependent Claim
190 words
In an integrated component located on a chip, said integrated component comprising a processor and an apparatus for detecting events which occur on the integrated component, said apparatus for detecting events comprising: trigger decode logic comprising; a plurality of inputs for receiving signals indicative of occurrences of events, and a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting the first output trigger signal when at least one event identified by the first event select register occurs, a first level detector for detecting a duration of at least one event, a first edge detector for detecting the occurrences of at least one event, and a first edge/level select for selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event; and counter logic for counting a number of first output trigger signals generated comprising; an input coupled to receive the first output trigger signal, and a count incrementor for selectively incrementing a first count for each first output trigger signal received.
Claim 25
Dependent Claim
190 words
In an integrated component located on a chip, said integrated component comprising a processor and an apparatus for detecting events which occur on the integrated component, said apparatus for detecting events comprising: trigger decode logic comprising; a plurality of inputs for receiving signals indicative of occurrences of events, and a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting the first output trigger signal when at least one event identified by the first event select register occurs, a first level detector for detecting a duration of at least one event, a first edge detector for detecting the occurrences of at least one event, and a first edge/level select for selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event; and counter logic for counting a number of first output trigger signals generated comprising; an input coupled to receive the first output trigger signal, and a count incrementor for selectively incrementing a first count for each first output trigger signal received.
Claim 26
Dependent Claim
31 words
The apparatus as set forth in claim 23, wherein said counter logic further comprises an output signal generator for generating an event signal when the first count reaches a predetermined value.
Claim 27
Dependent Claim
137 words
The apparatus as set forth in claim 23, wherein said trigger decode logic further comprises; a second event select register comprising data which identifies selectively events to generate a second trigger signal, said trigger decode logic outputting a second output trigger signal when at least one event identified by the second event select register occurs, a second level detector for detecting the duration of at least one event, a second edge detector for detecting the occurrences of at least one event, and a second edge/level select for selecting the second output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event; and said counter logic further comprising a second counter incrementor for selectively incrementing a second count for each second output trigger signal received.
Claim 28
Dependent Claim
31 words
The apparatus as set forth in claim 25, said counter logic further comprising trigger combination logic for selectively generating art event signal when the first count and second countreach predetermined values.
Claim 29
Dependent Claim
46 words
The apparatus as set forth in claim 26, wherein: said trigger combination logic comprises providing an input event signal to the trigger decode logic when the second count reaches a determined value; such that a cascaded count of events to generate the event signal is performed.
Claim 30
Dependent Claim
57 words
The apparatus as set forth in claim 27, further comprising logic to hold the input event signal indicative that the second count reached a determined value such that a first output trigger signal is generated for multiple clock cycles after an initial generation of the input event signal indicative that the second count reached a determined value.
Claim 31
Dependent Claim
54 words
The apparatus as set forth in claim 25, wherein the counter logic further comprises a first and second count output from which the first and second count of events stored m the counter logic are read, said processor further comprising logic to read the first count and second count output to gain performance information.
Claim 32
Dependent Claim
27 words
The apparatus as set forth in claim 29, said processor combining the first count and second count to determine an average occurrence of at least one event.
Claim 33
Dependent Claim
27 words
The apparatus as set forth in claim 29, said processor combining the first count and second count to determine an average duration of at least one event.
Claim 34
Dependent Claim
105 words
In an integrated component comprising a processor, said integrated component located on a chip a method executed on the integrated component for detecting events which occur on the integrated component comprising the step of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first output trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; storing the first count in a first counter register; and generating an event signal when the first count overflows the first counter register.
Claim 35
Dependent Claim
105 words
In an integrated component comprising a processor, said integrated component located on a chip a method executed on the integrated component for detecting events which occur on the integrated component comprising the step of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first output trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; storing the first count in a first counter register; and generating an event signal when the first count overflows the first counter register.
Claim 36
Dependent Claim
29 words
The method as set forth in claim 32, further comprising the step of programming the first count such that an event signal is generated when a programmed count occurs.
Claim 37
Dependent Claim
36 words
The method as set forth in claim 32, further comprising the step of loading a predetermined count into the first counter register such that an event signal is generated when a programmed count of triggers occurs.
Claim 38
Dependent Claim
26 words
The method as set forth in claim 32, further comprising the step of selectively logically ANDing or logically ORing signal identifying each selected event that occurs.
Claim 39
Dependent Claim
61 words
The method as set forth in claim 32, further comprising the steps of: selectively identifying events to generate a second trigger signal; outputting a second output trigger signal when at least one identified event occurs; incrementing a second count for each second output trigger signal received; and selectively generating the event signal when the first count and second countreach predetermined values.
Claim 40
Dependent Claim
46 words
The method as set forth in claim 36, furrier comprising the step of providing an input event signal to generate a first trigger signal when the second count reaches a determined value such that a cascaded count of events to generate the event signal is performed.
Claim 41
Dependent Claim
58 words
The method as set forth in claim 37, further comprising the step of holding the input event signal indicative that the second count reached a determined value such that a first output trigger signal is generated for multiple clock cycles after an initial generation of the input event signal indicative that the second count reached a determined value.
Claim 42
Dependent Claim
25 words
The method as set forth in claim 38, further comprising the step of combining the first count and second count to determine specific performance information.
Claim 43
Dependent Claim
97 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first output trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; generating an event signal to the processor when the first count reaches a predetermined value.
Claim 44
Dependent Claim
97 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first output trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; generating an event signal to the processor when the first count reaches a predetermined value.
Claim 45
Dependent Claim
29 words
The method as set forth in claim 40, further comprising the step of generating a trap to the processor on an instruction boundary upon generation of the event signal.
Claim 46
Dependent Claim
31 words
The method as set forth in claim 40, further comprising the step of generating a breakpoint to stop the processor on a dock cycle boundary when the event signal is generated.
Claim 47
Dependent Claim
28 words
The method as set forth in claim 42, further comprising the step of performing a scan of a state of the integrated component when a clock is stopped.
Claim 48
Dependent Claim
90 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first ought trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; reading the first count to determine performance information.
Claim 49
Dependent Claim
90 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; outputting a first ought trigger signal when at least one event selectively identified occurs; generating a first count of a number of output trigger signals generated; reading the first count to determine performance information.
Claim 50
Dependent Claim
26 words
The method as set forth in claim 44, wherein the step of reading the first count is performed periodically by the processor to determine performance information.
Claim 51
Dependent Claim
100 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; detecting a duration of at least one event; detecting an occurrence of at least one event and selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event.
Claim 52
Dependent Claim
100 words
In an integrated component comprising a processor, said integrated component located on a chip, a method executed on the integrated component for detecting events which occur on the integrated component comprising the steps of: receiving signals indicative of occurrences of events; selectively identifying events to generate a first output trigger signal when a selected event occurs; detecting a duration of at least one event; detecting an occurrence of at least one event and selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event.
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| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |