Patent US6684348B1 successfully refreshed from Google Patents.
US6684348B1
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Circuit for processing trace information
Assignee: Renesas Electronics Corp
•
Filing: 1999-10-01
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Granted: 2004-01-27
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Expires: 2019-10-01
Abstract
Abstract A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
Inventors
- 👤 David Alan Edwards
- 👤 Anthony Willis Rich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/3648
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
121 words
An integrated circuit chip comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor; and an interface for transmitting trace information off-chip, wherein the trace information is stored in compressed format and is transmitted off-chip, wherein the integrated circuit includes circuitry that compresses the trace information by at least one of a group of steps including: representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and representing timing information by a time difference.
Claim 2
Dependent Claim
121 words
An integrated circuit chip comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor; and an interface for transmitting trace information off-chip, wherein the trace information is stored in compressed format and is transmitted off-chip, wherein the integrated circuit includes circuitry that compresses the trace information by at least one of a group of steps including: representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and representing timing information by a time difference.
Claim 3
Dependent Claim
23 words
The integrated circuit according to claim 1 , wherein the trace information is buffered prior to storing the information in the FIFO buffer.
Claim 4
Dependent Claim
23 words
The integrated circuit according to claim 1 , wherein the trace information is filtered prior to storing the information in the FIFO buffer.
Claim 5
Dependent Claim
40 words
The integrated circuit according to claim 1 , wherein the trace information is selectively transmitted to at least one of: a memory circuit associated with the processor; and a link coupled to a debug system external to the debug module.
Claim 6
Dependent Claim
30 words
The integrated circuit according to claim 4 , wherein the debug module transmits to the processor a control signal to stall the processor when the FIFO approaches a full condition.
Claim 7
Dependent Claim
28 words
The integrated circuit according to claim 5 , wherein the debug module provides an indication to the external debug system that the FIFO is approaching the full condition.
Claim 8
Dependent Claim
29 words
The integrated circuit according to claim 5 , wherein the debug module provides an indication to the external debug system that an execution pipeline of the processor is stalled.
Claim 9
Dependent Claim
28 words
The integrated circuit according to claim 5 , wherein the debug module is configured in a trace hold mode wherein trace information is discarded when the FIFO fills.
Claim 10
Dependent Claim
28 words
The integrated circuit according to claim 1 , wherein the debug module transmits, in the trace information, an indication that one or more trace messages has been discarded.
Claim 11
Dependent Claim
22 words
The integrated circuit according to claim 7 , wherein the indication that the processor is stalled is included in a trace message.
Claim 12
Dependent Claim
45 words
The integrated circuit according to claim 1 , the processor sends a reference message including at least one of: timing information representing a time state of a processor process; a program counter of the processor; and an address of a device of a system bus.
Claim 13
Dependent Claim
20 words
The integrated circuit according to claim 1 , wherein the program counter is a shadowed program counter of a processor.
Claim 14
Dependent Claim
27 words
The integrated circuit according to claim 1 , wherein the trace information is generated from a circuit operatively coupled to a system bus of the computer system.
Claim 15
Dependent Claim
22 words
The integrated circuit according to claim 11 , wherein the processor generates a reference message within a predetermined number of time intervals.
Claim 16
Dependent Claim
29 words
The integrated circuit according to claim 11 , wherein the reference message is generated if a debug interface has been idle more than a specified number of time intervals.
Claim 17
Dependent Claim
18 words
The integrated circuit according to claim 11 , wherein the timing information is derived from a processor clock.
Claim 18
Dependent Claim
31 words
The integrated circuit according to claim 1 , wherein the time difference is a different in time from a current set of trace information to a previous set of trace information.
Claim 19
Dependent Claim
23 words
The integrated circuit according to claim 1 , wherein address offsets are determined by subtracting a previously sent address from a new address.
Claim 20
Dependent Claim
29 words
The integrated circuit according to claim 1 , wherein the trace information is encoded using absolute or relative encoding of at least one of address information and timing information.
Claim 21
Dependent Claim
122 words
An integrated circuit chip comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor; and means for transmitting trace information off-chip, wherein the trace information is stored in compressed format and transmitted off-chip, wherein the integrated circuit includes means for compressing the trace information, the means for compressing including at least one of: means for representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and means for representing timing information by a time difference.
Claim 22
Dependent Claim
122 words
An integrated circuit chip comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor; and means for transmitting trace information off-chip, wherein the trace information is stored in compressed format and transmitted off-chip, wherein the integrated circuit includes means for compressing the trace information, the means for compressing including at least one of: means for representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and means for representing timing information by a time difference.
Claim 23
Dependent Claim
27 words
The integrated circuit according to claim 20 , wherein the debug module includes means for buffering trace information prior to storing the information in the FIFO buffer.
Claim 24
Dependent Claim
28 words
The integrated circuit according to claim 20 , wherein the debug module includes means for filtering the trace information prior to storing the information in the FIFO buffer.
Claim 25
Dependent Claim
45 words
The integrated circuit according to claim 20 , wherein the integrated circuit includes means for selectively transmitting the trace information to at least one of: a memory circuit associated with the processor; and a link coupled to a debug system external to the debug module.
Claim 26
Dependent Claim
45 words
The integrated circuit according to claim 20 , the processor sends a reference message including at least one of: timing information representing a time state of a processor process; a program counter of the processor; and an address of a device of a system bus.
Claim 27
Dependent Claim
20 words
The integrated circuit according to claim 20 , wherein the program counter is a shadowed program counter of a processor.
Claim 28
Dependent Claim
27 words
The integrated circuit according to claim 20 , wherein the trace information is generated from an analyzer operatively coupled to a system bus of the computer system.
Claim 29
Dependent Claim
22 words
The integrated circuit according to claim 24 , wherein the processor generates a reference message within a predetermined number of time intervals.
Claim 30
Dependent Claim
29 words
The integrated circuit according to claim 24 , wherein the reference message is generated if a debug interface has been idle more than a specified number of time intervals.
Claim 31
Dependent Claim
18 words
The integrated circuit according to claim 24 , wherein the timing information is derived from a processor clock.
Claim 32
Dependent Claim
31 words
The integrated circuit according to claim 20 , wherein the time difference is a different in time from a current set of trace information to a previous set of trace information.
Claim 33
Dependent Claim
23 words
The integrated circuit according to claim 20 , wherein address offsets are determined by subtracting a previously sent address from a new address.
Claim 34
Dependent Claim
29 words
The integrated circuit according to claim 20 , wherein the trace information is encoded using absolute or relative encoding of at least one of address information and timing information.
Claim 35
Dependent Claim
30 words
The integrated circuit according to claim 20 , wherein the debug module transmits to the processor a control signal to stall the processor when the FIFO approaches a full condition.
Claim 36
Dependent Claim
28 words
The integrated circuit according to claim 33 , wherein the debug module provides an indication to the external debug system that the FIFO is approaching the full condition.
Claim 37
Dependent Claim
29 words
The integrated circuit according to claim 33 , wherein the debug module provides an indication to the external debug system that an execution pipeline of the processor is stalled.
Claim 38
Dependent Claim
29 words
The integrated circuit according to claim 33 , wherein the debug module is configured in a trace hold mode wherein trace information is discarded when the FIFO is full.
Claim 39
Dependent Claim
28 words
The integrated circuit according to claim 20 , wherein the debug module transmits, in the trace information, an indication that one or more trace messages have been discarded.
Claim 40
Dependent Claim
22 words
The integrated circuit according to claim 35 , wherein the indication that the processor is stalled is included in a trace message.
References Cited (Backward Citations)
EP0072092A2
Cited
EP0165660A1
Cited
EP0165600A2
Cited
US5440705A
Cited
US4814981A
Cited
US5251311A
Cited
US5386565A
Cited
US5452432A
Cited
US5355487A
Cited
US5682545A
Cited
US5423050A
Cited
US5724549A
Cited
US5479652A
Cited
US5479652B1
Cited
US5483518A
Cited
US5513317A
Cited
US5448576A
Cited
US5832248A
Cited
US5608881A
Cited
US5530965A
Cited
US5627842A
Cited
US5455936A
Cited
US5598551A
Cited
US5590354A
Cited
EP0636976A1
Cited
US5930523A
Cited
EP0652516A1
Cited
US5596734A
Cited
US5828825A
Cited
US5434804A
Cited
US5625785A
Cited
US5488688A
Cited
US5930833A
Cited
US5809293A
Cited
EP0702239A2
Cited
US5796978A
Cited
US5835963A
Cited
JPH08320796A
Cited
US5848247A
Cited
US5613153A
Cited
US5751621A
Cited
US5657273A
Cited
US5943498A
Cited
US5778237A
Cited
US5862387A
Cited
US5867726A
Cited
US5570375A
Cited
US5659679A
Cited
US5860127A
Cited
JPH08329687A
Cited
US5774701A
Cited
US5708773A
Cited
US6035422A
Cited
US5964893A
Cited
US5704034A
Cited
US5737516A
Cited
US5884092A
Cited
US5884023A
Cited
JPH09212358A
Cited
US5950012A
Cited
JPH09311786A
Cited
US5724505A
Cited
US5978874A
Cited
JPH10106269A
Cited
US6145099A
Cited
US5781558A
Cited
US5768152A
Cited
WO1998013759A1
Cited
JPH10124484A
Cited
JPH10177520A
Cited
US5918045A
Cited
US5848264A
Cited
US5983379A
Cited
US5983017A
Cited
US5953538A
Cited
US5771240A
Cited
US5956477A
Cited
US5996092A
Cited
US5999112A
Cited
US5983366A
Cited
US5896550A
Cited
US6154857A
Cited
US6314530B1
Cited
US6189140B1
Cited
US6185732B1
Cited
US6142683A
Cited
US6094729A
Cited
US6148381A
Cited
US6167536A
Cited
US5978902A
Cited
US5944841A
Cited
US6167499A
Cited
US6282701B1
Cited
US5938778A
Cited
US6175914B1
Cited
EP0933926A1
Cited
US6108761A
Cited
EP0945805A1
Cited
EP0959411A1
Cited
US6145123A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-01-26 | 2007-07-28 | 2008-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-01-26 | 2011-07-28 | 2012-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-01-26 | 2015-07-28 | 2016-01-27 | $7700.00 | Window Closed / Lapsed |