Patent US6551878B2 successfully refreshed from Google Patents.
US6551878B2
Expired / Lapsed
US
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Mini flash process and circuit
Assignee: Micron Technology Inc
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Filing: 2001-01-09
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Granted: 2003-04-22
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Expires: 2021-01-09
Abstract
Abstract A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.
Inventors
- 👤 Darwin A. Clampitt
- 👤 James E. Green
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:48
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 57
Claim 1
Independent Claim
157 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors, on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area; substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area.
Claim 2
Independent Claim
157 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors, on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area; substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area.
Claim 3
Dependent Claim
50 words
The method according to claim 1 , wherein the first dielectric layer is thicker than the second dielectric layer, and wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.
Claim 4
Dependent Claim
20 words
The method according to claim 2 , wherein the first chip area and the second chip area are substantially co-planar.
Claim 5
Independent Claim
195 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors that are to be used for signalling, and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors that are to be used for floating-gate memory; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area, substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing.
Claim 6
Independent Claim
195 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors that are to be used for signalling, and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors that are to be used for floating-gate memory; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area, substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing.
Claim 7
Independent Claim
256 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on both a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors, wherein the first dielectric layer is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages to be used for signalling; removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors, substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and covering the first dielectric layer and the second dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the second chip area.
Claim 8
Independent Claim
256 words
A method for fabricating an electronic circuit comprising: forming a first dielectric layer on both a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors, wherein the first dielectric layer is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages to be used for signalling; removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors, substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and covering the first dielectric layer and the second dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the second chip area.
Claim 9
Independent Claim
162 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area of a substrate to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; removing material to form a plurality of stack rows separated by isolation trenches, each of the isolation trenches substantially parallel to a first direction, wherein the isolation trenches extend into the substrate; depositing a nitride layer along at least side portions of the rows; substantially filling the isolation trenches with an insulator; removing material to form a plurality of columns separated by secondary trenches, each of the secondary trenches substantially perpendicular to the first direction, wherein the secondary trenches extend to the substrate; and depositing a nitride layer along at least side portions of the rows.
Claim 10
Independent Claim
162 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area of a substrate to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; removing material to form a plurality of stack rows separated by isolation trenches, each of the isolation trenches substantially parallel to a first direction, wherein the isolation trenches extend into the substrate; depositing a nitride layer along at least side portions of the rows; substantially filling the isolation trenches with an insulator; removing material to form a plurality of columns separated by secondary trenches, each of the secondary trenches substantially perpendicular to the first direction, wherein the secondary trenches extend to the substrate; and depositing a nitride layer along at least side portions of the rows.
Claim 11
Independent Claim
202 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench; depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Claim 12
Independent Claim
202 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench; depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Claim 13
Dependent Claim
50 words
The method according claim 7 , further comprising: forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end; forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and forming a tungsten gate contact to substantially contact the WSix layer.
Claim 14
Dependent Claim
21 words
The method according claim 8 , further comprising: forming an aluminum-copper (AlCu) line substantially in contact with the tungsten drain contact.
Claim 15
Independent Claim
212 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate; forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end; forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and forming a tungsten gate contact to substantially contact the WSix layer.
Claim 16
Independent Claim
212 words
A method for fabricating an electronic circuit comprising: forming a dielectric layer on a chip area to be used for a set of transistors; depositing a floating-gate poly layer over the dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate; forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end; forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and forming a tungsten gate contact to substantially contact the WSix layer.
Claim 17
Independent Claim
82 words
A method for fabricating an electronic circuit, the circuit having a substrate and a floating-gate stack on the substrate, the stack including a gate oxide on the substrate, and at least one poly layer on the gate oxide, the method comprising: etching a plurality of trenches through the stack, some of the trenches extending into the substrate, and others of the trenches stopping substantially at a top surface of the substrate; and depositing a nitride spacer layer on sides of the trenches.
Claim 18
Independent Claim
82 words
A method for fabricating an electronic circuit, the circuit having a substrate and a floating-gate stack on the substrate, the stack including a gate oxide on the substrate, and at least one poly layer on the gate oxide, the method comprising: etching a plurality of trenches through the stack, some of the trenches extending into the substrate, and others of the trenches stopping substantially at a top surface of the substrate; and depositing a nitride spacer layer on sides of the trenches.
Claim 19
Dependent Claim
23 words
The method according claim 11 , wherein the nitride spacer layer is deposited to isolate all sides of a floating gate poly layer.
Claim 20
Dependent Claim
96 words
The method according claim 11 , wherein the etching of the plurality of trenches comprises etching a first plurality of substantially parallel trenches through the stack into the substrate, the depositing of the nitride spacer layer comprises depositing nitride on sides of the first plurality of parallel trenches, the etching of the plurality of trenches further comprises etching a second plurality of substantially parallel trenches substantially perpendicular to the first plurality of substantially parallel trenches and the depositing of the nitride spacer layer further comprises depositing nitride on sides of the second plurality of parallel trenches.
Claim 21
Dependent Claim
40 words
The method according claim 13 , wherein the stack includes two poly layers separated by an inter-poly dielectric layer, and wherein the nitride spacer layer covers the sides of both poly layers and the sides of the inter-poly dielectric layer.
Claim 22
Independent Claim
287 words
A method for fabricating an electronic circuit, the circuit having a substrate, a gate oxide on the substrate, a floating-gate poly layer on the gate oxide, an inter-poly nitride layer on the floating gate poly layer, a control-gate poly layer on the inter-poly nitride layer; a tungsten-silicide (WSix) layer on the control-gate poly layer, and a nitride cap layer on the WSix layer; the method comprising: etching a plurality of isolation trenches along a first direction through the stack into the substrate; depositing a nitride spacer layer on sides of the isolation trenches; further etching to remove the nitride cap and to further deepen the plurality of isolation trenches into the substrate; filling the isolation trenches with tetraethylorthosilicate (TEOS); covering an area of the circuit with planarized borophosphosilicate glass (BPSG); etching lines along a second direction substantially perpendicular to the isolation trenches; depositing a nitride spacer layer on sides of the lines; covering the area of the circuit with a thin TEOS layer; covering the area of the circuit with planarized BPSG; etching trenches through the TEOS layer between adjacent transistors to the substrate and on portions of adjacent transistor areas to the WSix layer, using an etch that does not substantially etch nitride; depositing a titanium or titanium nitride barrier layer; filling the trench with tungsten; chemical-mechanical polishing (CMP) to planarize and remove tungsten and upper portions of oxide, stopping near tops of the nitride spacers; covering with BPSG, etching contacts through contact areas, depositing barrier layer in the contact areas, depositing tungsten in the contact areas, and chemical-mechanical polishing (CMP) back the tungsten to leave only the tungsten in the contact areas; and depositing aluminum copper (ALCU), etching interconnects, and covering with a passivation layer.
Claim 23
Independent Claim
287 words
A method for fabricating an electronic circuit, the circuit having a substrate, a gate oxide on the substrate, a floating-gate poly layer on the gate oxide, an inter-poly nitride layer on the floating gate poly layer, a control-gate poly layer on the inter-poly nitride layer; a tungsten-silicide (WSix) layer on the control-gate poly layer, and a nitride cap layer on the WSix layer; the method comprising: etching a plurality of isolation trenches along a first direction through the stack into the substrate; depositing a nitride spacer layer on sides of the isolation trenches; further etching to remove the nitride cap and to further deepen the plurality of isolation trenches into the substrate; filling the isolation trenches with tetraethylorthosilicate (TEOS); covering an area of the circuit with planarized borophosphosilicate glass (BPSG); etching lines along a second direction substantially perpendicular to the isolation trenches; depositing a nitride spacer layer on sides of the lines; covering the area of the circuit with a thin TEOS layer; covering the area of the circuit with planarized BPSG; etching trenches through the TEOS layer between adjacent transistors to the substrate and on portions of adjacent transistor areas to the WSix layer, using an etch that does not substantially etch nitride; depositing a titanium or titanium nitride barrier layer; filling the trench with tungsten; chemical-mechanical polishing (CMP) to planarize and remove tungsten and upper portions of oxide, stopping near tops of the nitride spacers; covering with BPSG, etching contacts through contact areas, depositing barrier layer in the contact areas, depositing tungsten in the contact areas, and chemical-mechanical polishing (CMP) back the tungsten to leave only the tungsten in the contact areas; and depositing aluminum copper (ALCU), etching interconnects, and covering with a passivation layer.
Claim 24
Independent Claim
132 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer the dielectric layer having a first thickness in a first area of the circuit and a second thickness, thinner than the first thickness, in a second area of the circuit; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; removing the inter-poly dielectric from the first area but not from the second area; and depositing a second poly gate layer over the inter-poly dielectric layer in the second area and on the first poly layer in the first area, wherein the second poly gate layer forms a control gate for a memory cell in the second area of the circuit.
Claim 25
Independent Claim
132 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer the dielectric layer having a first thickness in a first area of the circuit and a second thickness, thinner than the first thickness, in a second area of the circuit; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; removing the inter-poly dielectric from the first area but not from the second area; and depositing a second poly gate layer over the inter-poly dielectric layer in the second area and on the first poly layer in the first area, wherein the second poly gate layer forms a control gate for a memory cell in the second area of the circuit.
Claim 26
Dependent Claim
23 words
The method according claim 16 , further comprising: depositing a tungsten-silicide (WSix) layer over the second poly gate layer to reduce contact resistance.
Claim 27
Dependent Claim
62 words
The method according claim 16 , further comprising: depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.
Claim 28
Independent Claim
127 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; depositing a second poly gate layer over the inter-poly dielectric layer; removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer; depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.
Claim 29
Independent Claim
127 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; depositing a second poly gate layer over the inter-poly dielectric layer; removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer; depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.
Claim 30
Independent Claim
160 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area; substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area.
Claim 31
Independent Claim
160 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area; substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area.
Claim 32
Dependent Claim
37 words
The method according to claim 20 , wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.
Claim 33
Dependent Claim
50 words
The method according to claim 21 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; and depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.
Claim 34
Dependent Claim
189 words
The method according to claim 20 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench; depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Claim 35
Dependent Claim
76 words
The method according to claim 20 , comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack; and depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.
Claim 36
Independent Claim
185 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area, substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area; wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for at least one of programming and erasing.
Claim 37
Independent Claim
185 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area; forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area, substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area; wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for at least one of programming and erasing.
Claim 38
Dependent Claim
37 words
The method according to claim 25 , wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.
Claim 39
Dependent Claim
50 words
The method according to claim 26 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; and depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.
Claim 40
Dependent Claim
189 words
The method according to claim 25 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench; depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Claim 41
Dependent Claim
77 words
The method according to claim 25 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack; and depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.
Claim 42
Independent Claim
232 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors, substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area; wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and covering the first dielectric layer and the third dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the third chip area.
Claim 43
Independent Claim
232 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors, substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area; wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and covering the first dielectric layer and the third dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the third chip area.
Claim 44
Dependent Claim
37 words
The method according to claim 30 , wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.
Claim 45
Dependent Claim
50 words
The method according to claim 31 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; and depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.
Claim 46
Dependent Claim
189 words
The method according to claim 30 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench; depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Claim 47
Dependent Claim
77 words
The method according to claim 30 , further comprising: depositing a floating-gate polysilicon layer over the third dielectric layer; depositing an inter-poly nitride layer over the floating-gate polysilicon layer; depositing a control-gate polysilicon layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer; etching trenches to define a floating-gate stack; and depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.
Claim 48
Dependent Claim
26 words
The method according to claim 30 , further comprising: connecting the floating-gate stack as an electrically-erasable memory; and operably connecting the electrically-erasable memory to a microprocessor.
Claim 49
Dependent Claim
26 words
The method according to claim 30 , further comprising: connecting the floating-gate stack as an electrically-erasable memory; and operably connecting the electrically-erasable memory to a microprocessor.
Claim 50
Independent Claim
336 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area, wherein the first dielectric layer is thicker than the second dielectric layer, wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors that are formed by: depositing a floating-gate poly layer over the second dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate; forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end; forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and forming a tungsten gate contact to substantially contact the WSix layer.
Claim 51
Independent Claim
336 words
A method of fabricating an electronic circuit comprising: forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors; substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area, wherein the first dielectric layer is thicker than the second dielectric layer, wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors that are formed by: depositing a floating-gate poly layer over the second dielectric layer; depositing an inter-poly nitride layer over the floating-gate poly layer; depositing a control-gate poly layer over the inter-poly nitride layer; depositing a tungsten-silicide (WSix) layer over the control-gate poly layer; etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer; etching the stack to form a drain end and a source end; depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate; forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end; forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and forming a tungsten gate contact to substantially contact the WSix layer.
Claim 52
Independent Claim
145 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; depositing a second poly gate layer over the inter-poly dielectric layer; removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer; depositing a tungsten-silicide (WSix) layer over at least the second poly gate layer to reduce contact resistance; and depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.
Claim 53
Independent Claim
145 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; depositing a second poly gate layer over the inter-poly dielectric layer; removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer; depositing a tungsten-silicide (WSix) layer over at least the second poly gate layer to reduce contact resistance; and depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.
Claim 54
Independent Claim
105 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; removing the inter-poly dielectric from a first chip area but not from a second chip area; and depositing a second poly gate layer over the inter-poly dielectric layer in the second chip area, and on the first poly gate layer in the first chip area, wherein the second poly gate layer forms a control gate for a memory cell in the second chip area.
Claim 55
Independent Claim
105 words
A method for fabricating an electronic circuit on a wafer comprising: depositing a dielectric layer on a substrate of the wafer; depositing a first poly gate layer over the dielectric layer; depositing an inter-poly dielectric layer over the first poly layer; removing the inter-poly dielectric from a first chip area but not from a second chip area; and depositing a second poly gate layer over the inter-poly dielectric layer in the second chip area, and on the first poly gate layer in the first chip area, wherein the second poly gate layer forms a control gate for a memory cell in the second chip area.
Claim 56
Dependent Claim
23 words
The method according claim 39 , further comprising: depositing a tungsten-silicide (WSix) layer over the second poly gate layer to reduce contact resistance.
Claim 57
Dependent Claim
39 words
The method according claim 39 , further comprising: depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in the first chip area, and to the second poly gate layer in the second chip area.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-21 | 2006-10-21 | 2007-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-21 | 2010-10-21 | 2011-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-21 | 2014-10-21 | 2015-04-22 | $7700.00 | Window Closed / Lapsed |