US5656836A
Expired / Lapsed
US
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Semiconductor integrated circuit device and process for fabricating the same
Assignee: Renesas Electronics Corp
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Filing: 1995-06-02
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Granted: 1997-08-12
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Expires: 2015-06-02
Abstract
Abstract Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
Inventors
- 👤 Shuji Ikeda
- 👤 Satoshi Meguro
- 👤 Soichiro Hashiba
- 👤 Isamu Kuramoto
- 👤 Atsuyoshi Koike
- 👤 Katsuro Sasaki
- 👤 Koichiro Ishibashi
- 👤 Toshiaki Yamanaka
- 👤 Naotaka Hashimoto
- 👤 Nobuyuki Moriwaki
- 👤 Shigeru Takahashi
- 👤 Atsushi Hiraishi
- 👤 Yutaka Kobayashi
- 👤 Seigou Yukutake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:20
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10W20/40; H10W20/41; H10W20/427; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
403 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; and a static random access memory comprised of memory cells, each of said memory cells including a first and a second inverter circuit cross-coupled with one another, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, each of said memory cells further including a first transfer MISFET and a second transfer MISFET; each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as a drain region thereof, wherein said first region is formed between said second region and a channel forming region of said driver MISFET, wherein each of said transfer MISFETs has a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, wherein said third region is formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from a diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, wherein a diffusion coefficient of said third impurity is different from a diffusion coefficient of said fourth impurity, and wherein resistance contributed by said first region in a source-drain path of said driver MISFET is lower than resistance contributed by said third region in a source-drain path of said transfer MISFET.
Claim 2
Dependent Claim
403 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; and a static random access memory comprised of memory cells, each of said memory cells including a first and a second inverter circuit cross-coupled with one another, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, each of said memory cells further including a first transfer MISFET and a second transfer MISFET; each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as a drain region thereof, wherein said first region is formed between said second region and a channel forming region of said driver MISFET, wherein each of said transfer MISFETs has a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, wherein said third region is formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from a diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, wherein a diffusion coefficient of said third impurity is different from a diffusion coefficient of said fourth impurity, and wherein resistance contributed by said first region in a source-drain path of said driver MISFET is lower than resistance contributed by said third region in a source-drain path of said transfer MISFET.
Claim 3
Dependent Claim
42 words
A semiconductor memory device according to claim 1, wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 4
Dependent Claim
99 words
A semiconductor memory device according to claim 2, further comprising: first side wall spacers formed on side surfaces of said gate electrodes of said driver MISFETs; second side wall spacers formed on side surfaces of said gate electrodes of said transfer MISFETs, wherein said first region and said second region are formed in self-alignment with said first side wall spacer, wherein said first region surrounds said second region, wherein said third region is formed in self-alignment with said gate electrode of said transfer MISFET; and wherein said fourth region is formed in self-alignment with said second side wall spacer.
Claim 5
Dependent Claim
81 words
A semiconductor memory device according to claim 1, further comprising: first side wall spacers formed on side surfaces of said gate electrodes of said driver MISFETs; second side wall spacers formed on side surfaces of said gate electrodes of said transfer MISFETs, wherein said first region surrounds said second region, wherein said third region is formed in self-alignment with said gate electrode of said transfer MISFET; and wherein said fourth region is formed in self-alignment with said second side wall spacer.
Claim 6
Dependent Claim
61 words
A semiconductor memory device according to claim 1, further comprising: a MISFET for a peripheral circuit having a gate insulating film formed over said main surface, a gate electrode formed over said gate insulating film, and the same drain structure as said transfer MISFET, wherein said driver MISFET, said transfer MISFET, and said MISFET for said peripheral circuit are n-channel MISFETs.
Claim 7
Dependent Claim
42 words
A semiconductor memory device according to claim 5, wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 8
Dependent Claim
100 words
A semiconductor memory device according to claim 5, further comprising: first side wall spacers formed on side surfaces of said gate electrodes of said driver MISFETs; and second side wall spacers formed on side surfaces of said gate electrodes of said transfer MISFETs, wherein said first region and said second region are formed in self-alignment with said first side wall spacer, wherein said second region surrounds said first region, wherein said third region is formed in self-alignment with said gate electrode of said transfer MISFET; and wherein said fourth region is formed in self-alignment with said second side wall spacer.
Claim 9
Dependent Claim
38 words
A semiconductor memory device according to claim 5, wherein the resistance of said gate electrodes of said transfer MISFET and said MISFET for said peripheral circuit is lower than that of said gate electrode of said driver MISFET.
Claim 10
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein the resistance of said gate electrode of said transfer MISFET is lower than that of said gate electrode of said driver MISFET.
Claim 11
Dependent Claim
34 words
A semiconductor memory device according to claim 4, wherein said first and said second region are formed in self-alignment with said first side wall spacer, and wherein said first region surrounds said second region.
Claim 12
Dependent Claim
25 words
A semiconductor memory device according to claim 10, wherein said first region is doped with phosphorus, and wherein said second region is doped with arsenic.
Claim 13
Dependent Claim
42 words
A semiconductor memory device according to claim 10, wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 14
Dependent Claim
52 words
A semiconductor memory device according to claim 5, wherein the film thickness of the gate insulating film of said transfer MISFET and the film thickness of the gate insulating film of said MISFET for said peripheral circuit are greater than the film thickness of the gate insulating film of said driver MISFET.
Claim 15
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein the film thickness of the gate insulating film of said transfer MISFET is greater than the film thickness of the gate insulating film of said driver MISFET.
Claim 16
Dependent Claim
34 words
A semiconductor memory device according to claim 1, wherein said third region of said transfer MISFET has a size, under said gate electrode thereof, in a gate length direction thereof greater than 0.5 μm.
Claim 17
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein a maximum impurity concentration of said first impurity in said first region is greater than a maximum impurity concentration of said third impurity in said third region.
Claim 18
Dependent Claim
36 words
A semiconductor memory device according to claim 2, wherein a maximum impurity concentration of said first impurity in said first region is greater than a maximum impurity concentration of said third impurity in said third region.
Claim 19
Dependent Claim
32 words
A semiconductor memory device according to claim 17, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 20
Dependent Claim
32 words
A semiconductor memory device according to claim 16, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 21
Dependent Claim
32 words
A semiconductor memory device according to claim 1, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 22
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein drivability of said driver MISFET is greater than that of said transfer MISFET.
Claim 23
Dependent Claim
446 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; pairs of data lines, each pair being comprised of complementary data lines; a plurality of word lines; and a plurality of memory cells each including a first and a second inverter circuit cross-coupled with each other, a first transfer MISFET, and a second transfer MISFET, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, a source-drain path of said first transfer MISFET electrically coupled between a drain region of said first driver MISFET and one of said complementary data lines, a source-drain path of said second transfer MISFET electrically coupled between a drain region of said second driver MISFET and another of said complementary data lines, each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as said drain region thereof, said first region being formed between said second region and a channel forming region of said driver MISFET, each of said transfer MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, said gate electrode of said transfer MISFET being electrically coupled to said word line, and said third region being formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, and wherein a maximum impurity concentration of said first impurity in said first region is greater than a maximum impurity concentration of said third impurity in said third region.
Claim 24
Dependent Claim
446 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; pairs of data lines, each pair being comprised of complementary data lines; a plurality of word lines; and a plurality of memory cells each including a first and a second inverter circuit cross-coupled with each other, a first transfer MISFET, and a second transfer MISFET, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, a source-drain path of said first transfer MISFET electrically coupled between a drain region of said first driver MISFET and one of said complementary data lines, a source-drain path of said second transfer MISFET electrically coupled between a drain region of said second driver MISFET and another of said complementary data lines, each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as said drain region thereof, said first region being formed between said second region and a channel forming region of said driver MISFET, each of said transfer MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, said gate electrode of said transfer MISFET being electrically coupled to said word line, and said third region being formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, and wherein a maximum impurity concentration of said first impurity in said first region is greater than a maximum impurity concentration of said third impurity in said third region.
Claim 25
Dependent Claim
42 words
A semiconductor memory device according to claim 22, wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 26
Dependent Claim
99 words
A semiconductor memory device according to claim 22, further comprising: first side wall spacers formed on side surfaces of said gate electrodes of said driver MISFETs; second side wall spacers formed on side surfaces of said gate electrodes of said transfer MISFETs, wherein said first region and said second region are formed in self-alignment with said first side wall spacer, wherein said first region surrounds said second region, wherein said third region is formed in self-alignment with said gate electrode of said transfer MISFET; and wherein said fourth region is formed in self-alignment with said second side wall spacer.
Claim 27
Dependent Claim
36 words
A semiconductor memory device according to claim 22, wherein the film thickness of the gate insulating film of said transfer MISFET is greater than the film thickness of the gate insulating film of said driver MISFET.
Claim 28
Dependent Claim
22 words
A semiconductor memory device according to claim 22, wherein drivability of said driver MISFET is greater than that of said transfer MISFET.
Claim 29
Dependent Claim
32 words
A semiconductor memory device according to claim 22, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 30
Dependent Claim
32 words
A semiconductor memory device according to claim 23, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 31
Dependent Claim
451 words
A semiconductor device comprising: a semiconductor substrate having a main surface; pairs of data lines, each pair being comprised of complementary data lines; a plurality of word lines; and a plurality of memory cells each including a first and a second inverter circuit cross-coupled with each other, a first transfer MISFET, and a second transfer MISFET, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, a source-drain path of said first transfer MISFET electrically coupled between a drain region of said first driver MISFET and one of said complementary data lines, a source-drain path of said second transfer MISFET electrically coupled between a drain region of said second driver MISFET and another of said complementary data lines, each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as said drain region thereof, said first region being formed between said second region and a channel forming region of said driver MISFET, each of said transfer MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, said gate electrode of said transfer MISFET being electrically coupled to said word line, and said third region being formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, and wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 32
Dependent Claim
451 words
A semiconductor device comprising: a semiconductor substrate having a main surface; pairs of data lines, each pair being comprised of complementary data lines; a plurality of word lines; and a plurality of memory cells each including a first and a second inverter circuit cross-coupled with each other, a first transfer MISFET, and a second transfer MISFET, said first inverter circuit including a first driver MISFET and a first load element coupled in series, said second inverter circuit including a second driver MISFET and a second load element coupled in series, a source-drain path of said first transfer MISFET electrically coupled between a drain region of said first driver MISFET and one of said complementary data lines, a source-drain path of said second transfer MISFET electrically coupled between a drain region of said second driver MISFET and another of said complementary data lines, each of said driver MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a first and a second region formed in said semiconductor substrate and serving as said drain region thereof, said first region being formed between said second region and a channel forming region of said driver MISFET, each of said transfer MISFETs having a gate electrode formed over said main surface, a gate insulating film formed between said main surface and said gate electrode, and a third and a fourth region formed in said semiconductor substrate and serving as a drain region thereof, said gate electrode of said transfer MISFET being electrically coupled to said word line, and said third region being formed between said fourth region and a channel forming region of said transfer MISFET, wherein said second region is doped with a second impurity, wherein said first region is doped with a first impurity and is not doped with said second impurity such that a maximum impurity concentration of said first impurity in said first region is lower than a maximum impurity concentration of said second impurity in said second region, wherein a diffusion coefficient of said second impurity is different from diffusion coefficient of said first impurity, wherein said fourth region is doped with a fourth impurity, wherein said third region is doped with a third impurity and is not doped with said fourth impurity such that a maximum impurity concentration of said third impurity in said third region is lower than a maximum impurity concentration of said fourth impurity in said fourth region, and wherein said first region of said driver MISFET has a smaller size in a gate length direction thereof than a size, in a gate length direction of said transfer MISFET, of said third region.
Claim 33
Dependent Claim
32 words
A semiconductor memory device according to claim 29, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 34
Dependent Claim
99 words
A semiconductor memory device according to claim 29, further comprising: first side wall spacers formed on side surfaces of said gate electrodes of said driver MISFETs; second side wall spacers formed on side surfaces of said gate electrodes of said transfer MISFETs, wherein said first region and said second region are formed in self-alignment with said first side wall spacer, wherein said first region surrounds said second region, wherein said third region is formed in self-alignment with said gate electrode of said transfer MISFET; and wherein said fourth region is formed in self-alignment with said second side wall spacer.
Claim 35
Dependent Claim
32 words
A semiconductor memory device according to claim 31, wherein each of said first impurity and said third impurity is phosphorus, wherein each of said second impurity and said fourth impurity is arsenic.
Claim 36
Dependent Claim
22 words
A semiconductor memory device according to claim 29, wherein drivability of said driver MISFET is greater than that of said transfer MISFET.
References Cited (Backward Citations)
US4525811A
Cited
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