Cell structure for a programmable read only memory device

Claim 2

A semiconductor device having a plurality of cells, the cells comprising: a) a transistor source; b) a transistor drain; c) a transistor channel interposed between said source and said drain; d) a first layer formed of dielectric material; e) a second layer for storing a charge, said second layer having a first region which is heavily doped with an impurity and a second region which is lightly doped with an impurity, said first layer interposed between said transistor channel and said second layer, said first layer insulating said transistor channel from said second layer. f) a third layer formed of dielectric material; g) a fourth layer for selecting a plurality of cells, said third layer interposed between said second layer and said fourth layer, said third layer insulating said second layer from said fourth layer.

Claim 3

The device of claim 1 wherein said first region is located on a side of said second layer.

Claim 4

The device of claim 2 wherein said second layer further comprises a third region which is heavily doped.

Claim 5

The device of claim 3 wherein said first and third regions are located on opposite side of said second layer and said second region is interposed between said first and third regions.

Claim 6

The device of claim 1 wherein said first layer is less than 300Å thick.

Claim 7

The device of claim 1 wherein said first layer is between 100Å and 200Å thick.

Claim 8

The device of claim 1 wherein said first region is doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 and said second region is doped with an impurity to a concentration of between about 10 15 and 10 18 atoms/cm 3 .

Claim 9

The device of claim 1 wherein said second layer comprises polycrystalline silicon and said impurity is an element selected from the group consisting essentially of arsenic, phosphorous, and antimony.

Claim 10

A semiconductor device having a substrate and a plurality of cells formed by a process comprising the following steps: a) doping a first substrate region to form a transistor source; b) doping a second substrate region to form a transistor drain; c) providing a transistor channel interposed between said source and said drain; d) forming a first insulating layer over said channel; e) forming a first conductive layer over said channel; f) lightly doping said first conductive layer with an impurity to form a lightly doped region in said first layer; g) forming a second insulating layer over said first conductive layer; h) forming a second conductive layer over said first conductive layer; and i) angle doping a side of said first conductive layer to form a heavily doped region in said first conductive layer such that said heavily doped region has a different impurity concentration than said lightly doped region, whereby said heavily doped region in said first conductive layer provides a self-aligned tunneling window through said first insulating layer.

Claim 11

A semiconductor device having a substrate and a plurality of cells formed by a process comprising the following steps: a) doping a first substrate region to form a transistor source; b) doping a second substrate region to form a transistor drain; c) providing a transistor channel interposed between said source and said drain; d) forming a first insulating layer over said channel; e) forming a first conductive layer over said channel; f) lightly doping said first conductive layer with an impurity to form a lightly doped region in said first layer; g) forming a second insulating layer over said first conductive layer; h) forming a second conductive layer over said first conductive layer; and i) angle doping a side of said first conductive layer to form a heavily doped region in said first conductive layer such that said heavily doped region has a different impurity concentration than said lightly doped region, whereby said heavily doped region in said first conductive layer provides a self-aligned tunneling window through said first insulating layer.

Claim 12

The device of claim 9 further comprising the step of angle implanting a second side of said first conductive layer such that said first conductive layer has a lightly doped region interposed between two heavily doped regions.

Claim 13

The device of claim 9 further comprising the step of heavily doping an upper surface of said first conductive layer before the step of providing said second conductive layer.

Claim 14

The device of claim 9 wherein said heavily doped region of said first conductive layer is doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 and said lightly doped region of said first conductive layer is doped with an impurity to a concentration of between about 10 15 and 10 18 atoms/cm 3 .

Claim 15

A programmable memory device having a plurality of cells, the cells comprising: a) a transistor source; b) a transistor drain; c) a transistor channel interposed between said source and said drain; d) a floating gate, said floating having a first region which is doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 and a second region which is doped with an impurity to a concentration of between about 10 15 and 10 18 atoms/cm 3 , said first region having a different impurity concentration than said second region; e) a second layer interposed between said transistor channel and said first layer, said second layer insulating said transistor channel from said floating gate; and f) a control gate over said floating age and insulated therefrom, said control gate doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 .

Claim 16

A programmable memory device having a plurality of cells, the cells comprising: a) a transistor source; b) a transistor drain; c) a transistor channel interposed between said source and said drain; d) a floating gate, said floating having a first region which is doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 and a second region which is doped with an impurity to a concentration of between about 10 15 and 10 18 atoms/cm 3 , said first region having a different impurity concentration than said second region; e) a second layer interposed between said transistor channel and said first layer, said second layer insulating said transistor channel from said floating gate; and f) a control gate over said floating age and insulated therefrom, said control gate doped with an impurity to a concentration of between about 10 18 and 10 22 atoms/cm 3 .

Claim 17

The device of claim 13 wherein said first region is located on a side of said floating gate.

Claim 18

The device of claim 14 wherein said floating gate further comprises a third region which is doped to a concentration of between about 10 18 and 10 22 atoms/cm 3 .

Claim 19

The device of claim 15 wherein said first and third regions are located on opposite sides of said floating gate said second region is interposed between said first and third regions.

Claim 20

The device of claim 13 wherein said second layer is less than 300Å thick.

Claim 21

The device of claim 13 wherein said second layer is between 100Å and 200Å thick.

Claim 22

The device of claim 13 wherein said floating and control gates comprise polycrystalline silicon and said impurity is an element selected from the group consisting essentially of arsenic, phosphorous, and antimony.

Claim 23

A semiconductor device having a substrate and a plurality of cells formed by a process comprising the following steps: a) doping a first substrate region to form a transistor source; b) doping a second substrate region to form a transistor drain; c) providing a transistor channel interposed between said source and said drain; d) forming a first insulating layer over said channel; e) forming a first conductive layer over said channel; f) lightly doping said first conductive layer with an impurity to form a lightly doped region in said first conductive layer; g) forming a second insulating layer over said first conductive layer; h) forming a second conductive layer over said first conductive layer; and i) angle implanting said first conductive layer to form a heavily doped region in said first conductive layer, said lightly doped region having a different impurity concentration than said heavily doped region, whereby said heavily doped region in said first conductive layer provides a self-aligned tunneling window through said first insulating layer.

Claim 24

A semiconductor device having a substrate and a plurality of cells formed by a process comprising the following steps: a) doping a first substrate region to form a transistor source; b) doping a second substrate region to form a transistor drain; c) providing a transistor channel interposed between said source and said drain; d) forming a first insulating layer over said channel; e) forming a first conductive layer over said channel; f) lightly doping said first conductive layer with an impurity to form a lightly doped region in said first conductive layer; g) forming a second insulating layer over said first conductive layer; h) forming a second conductive layer over said first conductive layer; and i) angle implanting said first conductive layer to form a heavily doped region in said first conductive layer, said lightly doped region having a different impurity concentration than said heavily doped region, whereby said heavily doped region in said first conductive layer provides a self-aligned tunneling window through said first insulating layer.