US5720031A
Expired / Lapsed
US
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Method and apparatus for testing memory devices and displaying results of such tests
Assignee: Micron Technology Inc
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Filing: 1995-12-04
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Granted: 1998-02-17
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Expires: 2015-12-04
Abstract
Abstract An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested.
Inventors
- 👤 Brent Lindsay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:21
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/44
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
245 words
In a testing system for testing a semiconductor memory device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of memory locations each addressable by logical addresses, the apparatus comprising: an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data written to the plurality of memory locations in the semiconductor device and data read from the plurality of memory locations, each memory cell of the error catch memory being addressable by a physical address; a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of memory locations in the semiconductor device to selected memory cells in the error catch memory; and a programmable topological circuit coupled to error catch memory and the computer, the programmable topological circuit receiving spatial addresses from the computer, converting selected spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
Claim 2
Dependent Claim
245 words
In a testing system for testing a semiconductor memory device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of memory locations each addressable by logical addresses, the apparatus comprising: an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data written to the plurality of memory locations in the semiconductor device and data read from the plurality of memory locations, each memory cell of the error catch memory being addressable by a physical address; a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of memory locations in the semiconductor device to selected memory cells in the error catch memory; and a programmable topological circuit coupled to error catch memory and the computer, the programmable topological circuit receiving spatial addresses from the computer, converting selected spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1 wherein the programmable router circuit is a field programmable gate array.
Claim 4
Dependent Claim
41 words
The apparatus of claim 2 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the memory locations in the semiconductor memory device.
Claim 5
Dependent Claim
16 words
The apparatus of claim 1 wherein the programmable topological circuit is a field programmable gate array.
Claim 6
Dependent Claim
43 words
The apparatus of claim 2 wherein the programmable topological circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the plurality of memory cells in the error catch memory.
Claim 7
Dependent Claim
29 words
The apparatus of claim 1 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.
Claim 8
Dependent Claim
26 words
The apparatus of claim 1 wherein topological circuit is a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.
Claim 9
Independent Claim
187 words
A method of testing a semiconductor memory device and displaying on a display device spatial locations of errors in the semiconductor device, the semiconductor device having a plurality of memory locations each addressable by logical row and column address signals, the method comprising the steps of: loading a routing routine into a routing circuit for converting the logical addresses of the semiconductor device to physical addresses, the routing routine being based on a layout of the memory locations in the semiconductor memory device; loading a mapping routine into a topological circuit for converting spatial addresses to physical addresses, the mapping routine being based on a layout of a plurality of memory cells in a error catch memory; continually applying a test pattern to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error catch memory based on the routing routine; and substantially simultaneous with the step of continually applying a test pattern, constantly reading the error data from the error catch memory and displaying the error data at spatial locations on the display device based on the mapping routine.
Claim 10
Independent Claim
187 words
A method of testing a semiconductor memory device and displaying on a display device spatial locations of errors in the semiconductor device, the semiconductor device having a plurality of memory locations each addressable by logical row and column address signals, the method comprising the steps of: loading a routing routine into a routing circuit for converting the logical addresses of the semiconductor device to physical addresses, the routing routine being based on a layout of the memory locations in the semiconductor memory device; loading a mapping routine into a topological circuit for converting spatial addresses to physical addresses, the mapping routine being based on a layout of a plurality of memory cells in a error catch memory; continually applying a test pattern to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error catch memory based on the routing routine; and substantially simultaneous with the step of continually applying a test pattern, constantly reading the error data from the error catch memory and displaying the error data at spatial locations on the display device based on the mapping routine.
Claim 11
Dependent Claim
65 words
The method of claim 8, further comprising the steps of: determining a pattern for the row and column addresses of the memory locations in the semiconductor memory device, and determining an optimal routing routine for converting the logical addresses of the semiconductor device to physical addresses based on the pattern for the row and column addresses of the memory locations in the semiconductor memory device.
Claim 12
Dependent Claim
61 words
The method of claim 8, further comprising the steps of: determining a pattern for the row and column addresses of the memory cells in the error catch memory, and determining an optimal mapping routine for mapping the spatial addresses to physical addresses based on the pattern for the row and column addresses of the memory cells in the error catch memory.
Claim 13
Dependent Claim
26 words
The method of claim 8 wherein the step of loading a routing routine into a routing circuit loads a routine into a field programmable gate array.
Claim 14
Dependent Claim
26 words
The method of claim 8 wherein the step of loading a mapping routine into a topological circuit loads a routine into a field programmable gate array.
Claim 15
Dependent Claim
38 words
The method of claim 8 wherein the step of loading a routing routine into a routing circuit loads a routine into a read only memory that stores a look-up table for converting the logical addresses to physical addresses.
Claim 16
Dependent Claim
37 words
The method of claim 8 wherein the step of loading a mapping routine into a topological circuit loads a routine into a read only memory that stores a look-up table for converting spatial addresses to physical addresses.
Claim 17
Dependent Claim
218 words
In a testing system for testing a semiconductor device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of circuit locations each addressable by logical addresses, the apparatus comprising: an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, each memory cell of the error catch memory being addressable by a physical address; and a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of circuit locations in the semiconductor device to selected memory cells in the error catch memory, the error catch memory providing error data corresponding to selected physical addresses to the computer in response to spatial addresses from the computer to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
Claim 18
Dependent Claim
218 words
In a testing system for testing a semiconductor device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of circuit locations each addressable by logical addresses, the apparatus comprising: an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, each memory cell of the error catch memory being addressable by a physical address; and a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of circuit locations in the semiconductor device to selected memory cells in the error catch memory, the error catch memory providing error data corresponding to selected physical addresses to the computer in response to spatial addresses from the computer to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
Claim 19
Dependent Claim
240 words
A testing apparatus for testing a semiconductor device formed on a wafer, the semiconductor device having a plurality of memory circuits addressable by predetermined logical addresses, the apparatus comprising: a computer having a display device, the computer capable of having test data written to, and data read from, the plurality of memory circuits in the semiconductor device based on the predetermined logical addresses; an interface circuit for intercoupling to the semiconductor device and the computer; a comparator circuit coupled to the semiconductor device for comparing the test data written to the plurality of memory circuits to the data read from the plurality of memory circuits and producing error data in response to such comparison, the computer capable of displaying the error data at predetermined spatial addresses on the display device; and a mapping circuit having an error catch memory having a plurality of memory cells for storing the error data, the plurality of memory cells being addressable by physical addresses, a programmable router circuit coupled between the computer and the comparator circuit, and the error catch memory, the programmable router circuit converting the logical addresses to physical addresses to thereby route the error data to selected memory cells in the error catch memory, and a programmable topological circuit coupled between the computer and the error catch memory for converting the physical addresses to spatial addresses to thereby allow the error data to map to spatial addresses on the display device.
Claim 20
Dependent Claim
240 words
A testing apparatus for testing a semiconductor device formed on a wafer, the semiconductor device having a plurality of memory circuits addressable by predetermined logical addresses, the apparatus comprising: a computer having a display device, the computer capable of having test data written to, and data read from, the plurality of memory circuits in the semiconductor device based on the predetermined logical addresses; an interface circuit for intercoupling to the semiconductor device and the computer; a comparator circuit coupled to the semiconductor device for comparing the test data written to the plurality of memory circuits to the data read from the plurality of memory circuits and producing error data in response to such comparison, the computer capable of displaying the error data at predetermined spatial addresses on the display device; and a mapping circuit having an error catch memory having a plurality of memory cells for storing the error data, the plurality of memory cells being addressable by physical addresses, a programmable router circuit coupled between the computer and the comparator circuit, and the error catch memory, the programmable router circuit converting the logical addresses to physical addresses to thereby route the error data to selected memory cells in the error catch memory, and a programmable topological circuit coupled between the computer and the error catch memory for converting the physical addresses to spatial addresses to thereby allow the error data to map to spatial addresses on the display device.
Claim 21
Dependent Claim
32 words
The testing apparatus of claim 16, further comprising: a test bed for releasable securing the wafer; and a plurality of test probes for electrically intercoupling between the device and the interface circuit.
Claim 22
Dependent Claim
28 words
The testing apparatus of claim 16, further comprising an optical inspection device positioned over the test bed for allowing optical inspection of an upper surface of the wafer.
Claim 23
Dependent Claim
16 words
The apparatus of claim 16 wherein the programmable router circuit is a field programmable gate array.
Claim 24
Dependent Claim
41 words
The apparatus of claim 16 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the memory circuits in the semiconductor memory device.
Claim 25
Dependent Claim
16 words
The apparatus of claim 16 wherein the programmable topological circuit is a field programmable gate array.
Claim 26
Dependent Claim
43 words
The apparatus of claim 16 wherein the programmable topological circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the plurality of memory cells in the error catch memory.
Claim 27
Dependent Claim
29 words
The apparatus of claim 16 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.
Claim 28
Dependent Claim
26 words
The apparatus of claim 16 wherein topological circuit is a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-16 | 2001-08-18 | 2002-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-16 | 2005-08-18 | 2006-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-16 | 2009-08-18 | 2010-02-17 | $7700.00 | Window Closed / Lapsed |