High speed fail processor

Claim 1

Apparatus for testing a node of a circuit under test comprising a high-speed formatter including means for generating a high-speed test signal for application to a driver connected to said node in response to test pattern information received from a pattern generator, means for receiving a high-speed detected test signal from a detector connected to said node, and means for generating two half-speed detected test signals that contain alternate cycles of said high-speed detected test signal, first and second fail processor means connected to said high-speed formatter to receive respective half-speed detected signals for generating and outputting failure information based upon the states of cycles of said half-speed detected test signals, said failure information outputted by a particular fail processor means relating to specific, but not necessarily all, cycles of its respective half-speed detected test signal, first and second fail memory means connected to respective said first and second fail processor means for receiving said failure information from respective said fail processor means and for storing said failure information for specific cycles received from said fail processor means in successive memory locations, and sequence means for storing information indicating the sequence in which failure information is stored in said first and second fail memory means.