Patent US4057160A successfully refreshed from Google Patents.
US4709366A
Expired / Lapsed
US
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Computer assisted fault isolation in circuit board testing
Assignee: Fluke Corp
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Filing: 1985-07-29
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Granted: 1987-11-24
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Expires: 2005-07-29
Abstract
Abstract Circuit faults in an electronic system are isolated by a programmed computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the UUT. The measured response is compared to a predetermined response corresponding to an operational UUT to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the UUT. The computer is further programmed to have a form of "intuition" whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of UUT.
Inventors
- 👤 Marshall H. Scott
- 👤 John D. Polstra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/2257; Y; Y10; Y10S; Y10S706/00; Y10S706/902; Y10S706/911; Y10S706/916
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
237 words
A system for isolating circuit faults in a unit under test (UUT) including a circuit board to which are connected electronic components interconnected at circuit nodes on a bidirectional bus, the system comprising: generator means for generating first stimulus pattern signals for exercising nodes of said UUT in one direction of said bidirectional bus and for generating second stimulus pattern signals for exercising nodes of said UUT in an opposite direction of said bidirectional bus; interface means for applying the stimulus pattern signals to the UUT; measurement means responsive to the direction of said bidirectional bus through which nodes are exercised for measuring responses of the UUT to the first or second stimulus pattern signals at the circuit nodes; programmed computer means having memory means storing circuit topology data of the UUT, predetermined stimulus pattern signals associated with various circuit nodes of the UUT and responses expected from those nodes; said computer means including means for controlling said generator means to generate selectively said first and second stimulus pattern signals depending upon the particular circuit node responses being measured by said measurement means, comparing measured and predetermined responses and, in response, isolating circuit faults; data entry means for entering into said computer means data identifying circuit nodes being measured by said measurement means; and means responsive to said computer means for guiding said measurement means to appropriate nodes to be measured and for making circuit fault accusations.
Claim 2
Independent Claim
237 words
A system for isolating circuit faults in a unit under test (UUT) including a circuit board to which are connected electronic components interconnected at circuit nodes on a bidirectional bus, the system comprising: generator means for generating first stimulus pattern signals for exercising nodes of said UUT in one direction of said bidirectional bus and for generating second stimulus pattern signals for exercising nodes of said UUT in an opposite direction of said bidirectional bus; interface means for applying the stimulus pattern signals to the UUT; measurement means responsive to the direction of said bidirectional bus through which nodes are exercised for measuring responses of the UUT to the first or second stimulus pattern signals at the circuit nodes; programmed computer means having memory means storing circuit topology data of the UUT, predetermined stimulus pattern signals associated with various circuit nodes of the UUT and responses expected from those nodes; said computer means including means for controlling said generator means to generate selectively said first and second stimulus pattern signals depending upon the particular circuit node responses being measured by said measurement means, comparing measured and predetermined responses and, in response, isolating circuit faults; data entry means for entering into said computer means data identifying circuit nodes being measured by said measurement means; and means responsive to said computer means for guiding said measurement means to appropriate nodes to be measured and for making circuit fault accusations.
Claim 3
Dependent Claim
43 words
The system of claim 1, wherein said measurement means comprises a manual probe and said guiding means includes display means for displaying user prompts generated by said computer means to guide the user to probe appropriate nodes and for displaying circuit fault accusations.
Claim 4
Dependent Claim
15 words
The system of claim 2, wherein said display means comprises a cathode ray tube (CRT).
Claim 5
Dependent Claim
17 words
The system of claim 1, including a serial interface between said computer means and said generator means.
Claim 6
Dependent Claim
24 words
The system of claim 1, wherein said memory means includes means storing data describing characteristics of said components and the connections between said components.
Claim 7
Dependent Claim
26 words
The system of claim 5, wherein said memory means further includes means storing a history of nodes measured and a good/bad status of each node measured.
Claim 8
Dependent Claim
39 words
The system of claim 5, wherein said memory means further includes means storing data representative of circuit fault clues associated with functional testing of said UUT, said display means being responsive to said computer means for displaying said clues.
Claim 9
Dependent Claim
53 words
The system of claim 5, wherein said memory means further includes means storing identification of first and last circuit node failure associated with fault accusations encountered during previous testing; and means for controlling said display means to identify the last node when the first node is the only node determined to be "bad".
Claim 10
Independent Claim
167 words
A system for isolating circuit faults in a unit under test (UUT) including a circuit board to which are connected electronic components interconnected at circuit nodes, the system comprising: generator means for generating stimulus pattern signals for functional testing of said UUT; interface means for applying the pattern stimulus signals to the UUT; measurement probe means for measuring responses of the UUT to the stimulus signals at the circuit nodes; programmed computer means having memory means storing circuit topology data of the UUT and responses expected from the circuit nodes, said computer means including means for controlling said generator means and, in response to measured and expected responses, identifying circuit faults; said computer means including further memory means storing accumulations of first and last circuit node failures associated with particular fault accusations encountered during previous testing and means for identifying said last node when the first node is tested "bad"; and display means for displaying the identity of the last node as a node to be probed.
Claim 11
Independent Claim
167 words
A system for isolating circuit faults in a unit under test (UUT) including a circuit board to which are connected electronic components interconnected at circuit nodes, the system comprising: generator means for generating stimulus pattern signals for functional testing of said UUT; interface means for applying the pattern stimulus signals to the UUT; measurement probe means for measuring responses of the UUT to the stimulus signals at the circuit nodes; programmed computer means having memory means storing circuit topology data of the UUT and responses expected from the circuit nodes, said computer means including means for controlling said generator means and, in response to measured and expected responses, identifying circuit faults; said computer means including further memory means storing accumulations of first and last circuit node failures associated with particular fault accusations encountered during previous testing and means for identifying said last node when the first node is tested "bad"; and display means for displaying the identity of the last node as a node to be probed.
Claim 12
Dependent Claim
155 words
In a system for testing a circuit board containing electronic components interconnected at circuit nodes, supplying signals to the nodes for exercising said nodes through bidirectional signal lines on the board; a guided fault isolation method, comprising the steps of: (a) functionally testing a circuit board to identify the existence of a fault within a functional portion of the circuit board; (b) applying to the bidirectional signal lines different diverse stimulus pattern signals depending upon the particular nodes being monitored and upon the direction through which said nodes are exercised in said bidirectional signal lines; (c) measuring responses at the circuit nodes with a measurement probe; (d) comparing measured responses with predetermined responses corresponding to said nodes and said diverse stimulus pattern signals; and, in response, (e) generating signals identifying subsequent nodes to be measured by said measurement probe; (f) identifying a source of the circuit fault; and (g) generating signals representing fault source accusations.
Claim 13
Dependent Claim
155 words
In a system for testing a circuit board containing electronic components interconnected at circuit nodes, supplying signals to the nodes for exercising said nodes through bidirectional signal lines on the board; a guided fault isolation method, comprising the steps of: (a) functionally testing a circuit board to identify the existence of a fault within a functional portion of the circuit board; (b) applying to the bidirectional signal lines different diverse stimulus pattern signals depending upon the particular nodes being monitored and upon the direction through which said nodes are exercised in said bidirectional signal lines; (c) measuring responses at the circuit nodes with a measurement probe; (d) comparing measured responses with predetermined responses corresponding to said nodes and said diverse stimulus pattern signals; and, in response, (e) generating signals identifying subsequent nodes to be measured by said measurement probe; (f) identifying a source of the circuit fault; and (g) generating signals representing fault source accusations.
Claim 14
Dependent Claim
41 words
The method of claim 10, including storing pairs of first and last nodes tested and associated failure accusations encountered during previous testing; and displaying and prompting an identification of the last node when the first node is determined to be "bad".
Claim 15
Dependent Claim
40 words
The method of claim 10, including storing a clue associated with a particular functional failure type determined during step (a) and displaying said clue to identify a priority of node responses to be measured to identify a first bad node.
Claim 16
Dependent Claim
17 words
The method of claim 10, including the step of storing a good/bad status of each node probed.
Claim 17
Dependent Claim
192 words
In a system for testing a circuit board containing electronic components interconnected at circuit nodes, a guided fault isolation method, comprising the steps of: (a) functionally testing a circuit board to identify the existence of a functional fault; (b) applying to the signal lines different stimulus pattern signals depending upon the particular nodes being monitored; (c) measuring responses at the circuit nodes with a measurement probe; (d) comparing measured response with predetermined responses corresponding to said nodes; and, in response, (e) generating signals identifying subsequent nodes to be measured by said measurment probe; (f) identifying a source of the circuit fault; (g) generating signals representing fault source accusations; (h) identifying a first bad node; (i) identifying a last bad node prior to generation of a fault source accusation; (j) storing a cumulative first:last bad node pair list for each UUT; (k) establishing a "hit ratio" representing an observed likelihood of the first node being paired with the last node; (l) classifying said last node as a "companion" of the first node if the "hit ratio" is greater than a predetermined ratio; and (m) generating a signal recommending probing of the companion node.
Claim 18
Dependent Claim
192 words
In a system for testing a circuit board containing electronic components interconnected at circuit nodes, a guided fault isolation method, comprising the steps of: (a) functionally testing a circuit board to identify the existence of a functional fault; (b) applying to the signal lines different stimulus pattern signals depending upon the particular nodes being monitored; (c) measuring responses at the circuit nodes with a measurement probe; (d) comparing measured response with predetermined responses corresponding to said nodes; and, in response, (e) generating signals identifying subsequent nodes to be measured by said measurment probe; (f) identifying a source of the circuit fault; (g) generating signals representing fault source accusations; (h) identifying a first bad node; (i) identifying a last bad node prior to generation of a fault source accusation; (j) storing a cumulative first:last bad node pair list for each UUT; (k) establishing a "hit ratio" representing an observed likelihood of the first node being paired with the last node; (l) classifying said last node as a "companion" of the first node if the "hit ratio" is greater than a predetermined ratio; and (m) generating a signal recommending probing of the companion node.
Claim 19
Dependent Claim
41 words
The method of claim 14, wherein step (k) includes determining the number of times that the first node is paired with the last node divided by the number of times that the first node is not paired with the last node.
References Cited (Backward Citations)
US4055801A
Cited
US4070565A
Cited
US4114093A
Cited
US4216539A
Cited
US4192451A
Cited
US4242751A
Cited
US4228537A
Cited
US4459695A
Cited
US4642561A
Cited
US4642561B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-23 | 1991-05-25 | 1991-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-23 | 1995-05-25 | 1995-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-23 | 1999-05-25 | 1999-11-24 | $7700.00 | Window Closed / Lapsed |