US5089867A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High control gate/floating gate coupling for EPROMs, E2 PROMs, and Flash E2 PROMs
Assignee: Micron Technology Inc
•
Filing: 1991-05-06
•
Granted: 1992-02-18
•
Expires: 2011-05-06
Abstract
Abstract Floating gates for EPROMs, E 2 PROMs, Flash E 2 PROMs, and other devices are texturized to provide more surface area than previous gate designs. Ruggedizing the upper surface of the floating gate causes texturization of an oxide-nitride-oxide layer formed superjacent to the floating gate, which causes texturization of the lower surface of the control gate formed thereupon resulting in increased coupling between the two gates. The oxide-nitride-oxide layer between the floating gate and control gate allows increased capacitance without allowing leakage of electrons between the two gates as would a layer of oxide which is normally used. The invention allows a smaller feature width, and therefore a higher density EPROM. Increased speed results from the reduced feature size.
Inventors
- 👤 Ruojia Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/01; H10D64/031; H10D64/035; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
144 words
A transistor memory cell for an electronic device, comprising: a) a substrate having spaced source and drain regions and a channel region therebetween; b) a first insulating layer disposed on said channel region; c) a floating gate disposed on said first insulating layer, a portion of said floating gate being positioned over said channel region, to for a first capacitor having a first capacitance with said substrate, said floating gate having a surface which is texturized, wherein said texturization of said floating gate surface increases the area of said surface; d) a second insulating layer disposed on said floating gate, wherein said second insulating layer prevents the tunneling of electrons between said floating gate and said control gate; and e) a control gate disposed on said second insulating layer, said control gate forming a second capacitor having a second capacitance with said floating gate.
Claim 2
Dependent Claim
144 words
A transistor memory cell for an electronic device, comprising: a) a substrate having spaced source and drain regions and a channel region therebetween; b) a first insulating layer disposed on said channel region; c) a floating gate disposed on said first insulating layer, a portion of said floating gate being positioned over said channel region, to for a first capacitor having a first capacitance with said substrate, said floating gate having a surface which is texturized, wherein said texturization of said floating gate surface increases the area of said surface; d) a second insulating layer disposed on said floating gate, wherein said second insulating layer prevents the tunneling of electrons between said floating gate and said control gate; and e) a control gate disposed on said second insulating layer, said control gate forming a second capacitor having a second capacitance with said floating gate.
Claim 3
Dependent Claim
12 words
The transistor memory cell of claim 1 wherein said substrate comprises silicon.
Claim 4
Dependent Claim
27 words
The transistor memory cell of claim 1 wherein said texturized surface of said floating gate is formed by the deposition of a material at a controlled temperature.
Claim 5
Dependent Claim
17 words
The transistor memory cell of claim 3 wherein said temperature is between 566° C. and 574° C.
Claim 6
Dependent Claim
25 words
The transistor memory cell of claim 1 wherein said texturized surface of said floating gate is formed by exposing said surface to a corrosive material.
Claim 7
Dependent Claim
14 words
The transistor memory cell of claim 5 wherein said corrosive material is hydrofluoric acid.
Claim 8
Dependent Claim
20 words
The transistor memory cell of claim 1 wherein the electronic device transfers electrons between said substrate and said floating gate.
Claim 9
Dependent Claim
14 words
The transistor memory cell of claim 7 wherein the electronic device is an EPROM.
Claim 10
Dependent Claim
16 words
The transistor memory cell of claim 7 wherein the electronic device is an E 2 PROM.
Claim 11
Dependent Claim
17 words
The transistor memory cell of claim 7 wherein the electronic device is a Flash E 2 EPROM.
Claim 12
Dependent Claim
15 words
The transistor memory cell of claim 1 wherein said second layer comprises oxide and nitride.
Claim 13
Dependent Claim
205 words
A transistor memory cell for an electronic device, comprising: a) a substrate having spaced source and drain regions and a channel region therebetween, said source, drain, and channel regions forming a transistor; b) a first insulating layer disposed on said channel region; c) a floating gate disposed on said first insulating layer, a portion of said floating gate being positioned over said channel region, to for a first capacitor having a first capacitance with said substrate, said floating gate having top and bottom surfaces wherein said top surface is texturized, wherein said texturization of said top surface of said floating gate increases the area of said top surface; d) a second insulating layer disposed on and conformal with said floating gate, said second insulating layer having texturized top and bottom surfaces thereby, wherein said second insulating layer prevents the tunneling of electrons between said floating gate and said control gate; and e) a control gate having top and bottom surfaces, said control gate being disposed on said second insulating layer, said bottom surface of said control gate being conformal with said second insulating layer top surface and being texturized thereby, and said control gate forming second capacitor having a second capacitance with said floating gate.
Claim 14
Dependent Claim
205 words
A transistor memory cell for an electronic device, comprising: a) a substrate having spaced source and drain regions and a channel region therebetween, said source, drain, and channel regions forming a transistor; b) a first insulating layer disposed on said channel region; c) a floating gate disposed on said first insulating layer, a portion of said floating gate being positioned over said channel region, to for a first capacitor having a first capacitance with said substrate, said floating gate having top and bottom surfaces wherein said top surface is texturized, wherein said texturization of said top surface of said floating gate increases the area of said top surface; d) a second insulating layer disposed on and conformal with said floating gate, said second insulating layer having texturized top and bottom surfaces thereby, wherein said second insulating layer prevents the tunneling of electrons between said floating gate and said control gate; and e) a control gate having top and bottom surfaces, said control gate being disposed on said second insulating layer, said bottom surface of said control gate being conformal with said second insulating layer top surface and being texturized thereby, and said control gate forming second capacitor having a second capacitance with said floating gate.
Claim 15
Dependent Claim
12 words
The transistor memory cell of claim 12 wherein said substrate comprises silicon.
Claim 16
Dependent Claim
25 words
The transistor memory cell of claim 12 wherein said floating gate is formed by depositing the material of said floating gate at a controlled temperature.
Claim 17
Dependent Claim
17 words
The transistor memory cell of claim 14 wherein said temperature is between 566° C. and 574° C.
Claim 18
Dependent Claim
25 words
The transistor memory cell of claim 12 wherein said top surface of said floating gate is texturized by exposing said surface to a corrosive material.
Claim 19
Dependent Claim
14 words
The transistor memory cell of claim 16 wherein said corrosive material is hydrofluoric acid.
Claim 20
Dependent Claim
20 words
The transistor memory cell of claim 12 wherein the electronic device transfers electrons between said substrate and said floating gate.
Claim 21
Dependent Claim
14 words
The transistor memory cell of claim 18 wherein the electronic device is an EPROM.
Claim 22
Dependent Claim
16 words
The transistor memory cell of claim 18 wherein the electronic device is an E 2 PROM.
Claim 23
Dependent Claim
17 words
The transistor memory cell of claim 18 wherein the electronic device is a Flash E 2 PROM.
Claim 24
Dependent Claim
14 words
The transistor memory cell of claim 12 wherein said material comprises oxide and nitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |