US5600602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hierarchical memory array structure having electrically isolated bit lines for temporary data storage
Assignee: Mosaid Technologies Inc
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Filing: 1995-04-05
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Granted: 1997-02-04
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Expires: 2015-04-05
Abstract
Abstract An integrated memory array circuit, such as a DRAM, has a global bit line communicating a global bit line signal with a first electrode of each of a plurality of FET devices. The primary global bit line has a plurality of subarray bit lines. Each subarray bit line communicates a subarray bit line signal with a second electrode of one of the FET devices and with a first electrode of each of a plurality of subarray FET devices. Each subarray FET device has a gate communicating a word line signal with a word line. Each subarray FET device has a second electrode communicating a one bit storage signal with a capacitor. Each subarray FET is activated by a word line signal from a corresponding word line to electrically isolate a corresponding capacitor from its corresponding subarray bit line, or to electrically connect the corresponding capacitor with its corresponding subarray bit line. A device senses and amplifies the global bit line signal and outputs an amplified global bit line signal to a column decode device. By using switches and FETs to electrically isolated memory array structure components, data can be temporarily stored on such components, including the device that amplifies the global bit line signal, the global bit line, each of the subarray bit lines, and each of the capacitors.
Inventors
- 👤 Mir M. Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
252 words
A method of storing data in a memory comprising: a plurality of subarray bit lines, each of the plurality of subarray bit lines having a capacitance selectively chosen for data storage; a plurality of memory storage capacitors; a plurality of addressable memory capacitor access devices connected to the plurality of memory storage capacitors for selectively coupling one of the plurality of memory storage capacitors to one of the plurality of subarray bit lines to charge share a memory capacitor charge with a subarray bit line charge; a global bit line having a capacitance; a plurality of addressable subarray bit line access devices connected to the global bit line and the plurality of subarray bit lines, the plurality of addressable subarray bit line access devices for either electrically isolating the plurality of subarray bit lines from the global bit line, or selectively coupling one of the plurality of subarray bit lines to the global bit line for charge sharing an un-amplified subarray bit line charge with the global bit line capacitance; and a sense amplifier circuit connected to the global bit line for sensing and amplifying a voltage on the global bit line, the method comprising the steps of: providing a charge on a first one of the plurality of subarray bit lines; electrically isolating the first one of the plurality of subarray bit lines from the global bit line and the plurality of memory storage capacitors to temporarily store the charge on the first one of the plurality of subarray bit lines.
Claim 2
Independent Claim
252 words
A method of storing data in a memory comprising: a plurality of subarray bit lines, each of the plurality of subarray bit lines having a capacitance selectively chosen for data storage; a plurality of memory storage capacitors; a plurality of addressable memory capacitor access devices connected to the plurality of memory storage capacitors for selectively coupling one of the plurality of memory storage capacitors to one of the plurality of subarray bit lines to charge share a memory capacitor charge with a subarray bit line charge; a global bit line having a capacitance; a plurality of addressable subarray bit line access devices connected to the global bit line and the plurality of subarray bit lines, the plurality of addressable subarray bit line access devices for either electrically isolating the plurality of subarray bit lines from the global bit line, or selectively coupling one of the plurality of subarray bit lines to the global bit line for charge sharing an un-amplified subarray bit line charge with the global bit line capacitance; and a sense amplifier circuit connected to the global bit line for sensing and amplifying a voltage on the global bit line, the method comprising the steps of: providing a charge on a first one of the plurality of subarray bit lines; electrically isolating the first one of the plurality of subarray bit lines from the global bit line and the plurality of memory storage capacitors to temporarily store the charge on the first one of the plurality of subarray bit lines.
Claim 3
Dependent Claim
123 words
The method of claim 1 wherein the method further comprises the step of: equilibrating the plurality of subarray bit lines to a predetermined voltage; electrically isolating the global bit line from the plurality of subarray bit lines; electrically isolating the plurality of subarray bit lines from the plurality of memory storage capacitors; amplifying data provided on the global bit line; selectively coupling the global bit line to a first one of the plurality of subarray bit lines and charge sharing the amplified data between the global bit line and the first one of the plurality of subarray bit lines; electrically isolating the global bit line from the first one of the plurality of subarray bit lines to temporarily store the charge shared data.
Claim 4
Dependent Claim
48 words
The method of claim 2 wherein the method further comprises the step of: selectively coupling the first one of the plurality of subarray bit lines with one of the plurality of memory storage capacitors to store the data in the one of the plurality of memory storage capacitors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |