US5295101A
Expired / Lapsed
US
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Array block level redundancy with steering logic
Assignee: Texas Instruments Inc
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Filing: 1992-01-31
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Granted: 1994-03-15
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Expires: 2012-01-31
Abstract
Abstract The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements. When activated for redundancy, the second level redundancy scheme replaces at least one defective sub-block of memory devices with a like number of redundant sub-blocks of memory devices.
Inventors
- 👤 Michael C. Stephens, Jr.
- 👤 Scott E. Smith
- 👤 Charles J. Pilch
- 👤 Duy-Loan T. Le
- 👤 Terry T. Tsai
- 👤 Arthur R. Piejko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:34
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/81; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
104 words
A memory device with one or more data blocks each having individual input-output paths, at least one data block comprising: an array of memory cells arranged along row lines and column lines and configured in sub-blocks each comprising a plurality of memory cells arranged in rows and columns; and support circuitry to read information from the memory cells and to write information into the memory cells, the support circuitry including redundancy circuitry for replacing at least one defective sub-block of memory cells with a like number of functional sub-blocks of memory cells, each sub-block of memory cells including redundant elements for replacing defective elements.
Claim 2
Dependent Claim
104 words
A memory device with one or more data blocks each having individual input-output paths, at least one data block comprising: an array of memory cells arranged along row lines and column lines and configured in sub-blocks each comprising a plurality of memory cells arranged in rows and columns; and support circuitry to read information from the memory cells and to write information into the memory cells, the support circuitry including redundancy circuitry for replacing at least one defective sub-block of memory cells with a like number of functional sub-blocks of memory cells, each sub-block of memory cells including redundant elements for replacing defective elements.
Claim 3
Dependent Claim
25 words
The memory device of claim 1 in which said redundant elements are redundant rows of memory cells for replacement of defective rows of memory cells.
Claim 4
Dependent Claim
15 words
The memory device of claim 2 in which there are four redundant rows per sub-block.
Claim 5
Dependent Claim
27 words
The memory device of claim 1 in which said redundancy circuitry selects four functional sub-blocks of memory cells for replacement of four sub-blocks of defective memory cells.
Claim 6
Dependent Claim
20 words
The memory device of claim 4 in which said four functional sub-blocks of memory cells are adjacent to each other.
Claim 7
Dependent Claim
26 words
The memory device of claim 1 in which said redundancy circuitry includes steering logic to redirect a replacement block I/O to an appropriate DQ (input/output) pin.
Claim 8
Dependent Claim
39 words
The memory device of claim 6 in which said steering logic includes defective section indicator signals for indicating that a deffective section has at least one sub-block with a defect that cannot be repaired using said sub-block's redundant elements.
Claim 9
Dependent Claim
63 words
The memory device of claim 7 including a multiplexer having a first input connected to a memory section, a second input connected to a redundant memory section, a third input for receiving a defective section indicator signal indicating that said memory section has a defect that cannot be repaired using said memory section's redundant elements and an output connected to a DQ pin.
Claim 10
Dependent Claim
62 words
The memory device of claim 8 in which said multiplexer couples said memory section to said DQ pin when said defective section indicator signal indicates no-defects and, in the alternative, couples said redundant memory section to said DQ pin when said defective section indicator signal indicates a defect in said memory section that cannot be repaired using said memory section's redundant elements.
Claim 11
Dependent Claim
134 words
A memory device with one or more data blocks each having individual input/output paths, one data block comprising: an array of memory cells arranged along row lines and column lines and configured in sub-blocks each comprising a plurality of memory cells arranged in rows and columns and also having redundant rows of memory cells to substitute for defective rows; support circuitry to read information from the memory cells and to write information into the memory cells, the support circuitry including: row redundant circuitry for replacing a defective row of memory cells with a redundant row of memory cells in only the sub-block having the defective row of memory cells; and block level redundant circuitry for replacing at least one defective sub-block of memory cells with a like number of functional sub-block of memory cells.
Claim 12
Dependent Claim
134 words
A memory device with one or more data blocks each having individual input/output paths, one data block comprising: an array of memory cells arranged along row lines and column lines and configured in sub-blocks each comprising a plurality of memory cells arranged in rows and columns and also having redundant rows of memory cells to substitute for defective rows; support circuitry to read information from the memory cells and to write information into the memory cells, the support circuitry including: row redundant circuitry for replacing a defective row of memory cells with a redundant row of memory cells in only the sub-block having the defective row of memory cells; and block level redundant circuitry for replacing at least one defective sub-block of memory cells with a like number of functional sub-block of memory cells.
Claim 13
Independent Claim
94 words
A method of repairing defects in a memory device, comprising the steps of: providing a first level of redundancy for at least one block of memory cells in said memory device, said at least one block of memory cells is divided into sub-blocks of memory cells and said first level of redundancy provides redundant elements for at least one of said sub-blocks of memory cells; and providing a second level of redundancy for said at least one block of memory cells that can be utilized once said first level of redundancy has been exhausted.
Claim 14
Independent Claim
94 words
A method of repairing defects in a memory device, comprising the steps of: providing a first level of redundancy for at least one block of memory cells in said memory device, said at least one block of memory cells is divided into sub-blocks of memory cells and said first level of redundancy provides redundant elements for at least one of said sub-blocks of memory cells; and providing a second level of redundancy for said at least one block of memory cells that can be utilized once said first level of redundancy has been exhausted.
Claim 15
Dependent Claim
13 words
The method of claim 11 in which said defects are defective memory cells.
Claim 16
Dependent Claim
16 words
The method of claim 12 in which said defective memory cells are defective row memory cells.
Claim 17
Dependent Claim
44 words
The method of claim 11 in which said second level of redundancy is a second block of memory cells that replaces said at least one block of memory cells having at least one defect that cannot be repaired using said first level of redundancy.
Claim 18
Dependent Claim
33 words
The method of claim 11 including defective section indicator signals for indicating that a defective section has at least one sub-block with a defect that cannot be repaired using said sub-block's redundant elements.
Claim 19
Dependent Claim
37 words
The method of claim 15 including steering logic for multiplexing between data from a defective section indicating that it has at least one sub-block with a defect that cannot be repaired and data from a replacing section.
Claim 20
Dependent Claim
69 words
The method of claim 16 in which said steering logic couples said block of memory cells to a selected DQ pin when said defective section indicator signal indicates no-defects and, in the alternative, couples said selected DQ pin to said replacing section when said defective section indicator signal indicates a defect in said block of memory cells that cannot be repaired using said block of memory cells' redundant elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |