US4888732A
Expired / Lapsed
US
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Dynamic random access memory having open bit line architecture
Assignee: Panasonic Holdings Corp
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Filing: 1988-02-18
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Granted: 1989-12-19
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Expires: 2008-02-18
Abstract
Abstract A dynamic random access memory which includes a sense amplifier, first pair of bit lines extending in the opposite directions from the sense amplifier, second pair of bit lines extending in the opposite directions from the sense amplifier and disposed in parallel with the first pair of bit lines, a plurality of word lines disposed in a manner that the word lines perpendicularly intersect with the first and second pairs of bit lines, and a plurality of memory cells disposed at all intersecting points of the word lines and the first and second pairs of bit lines. Two bit lines selected from the first and second pairs of bit lines are coupled to the sense amplifier. Since two bit lines or two groups of memory cells can be disposed at one side of the sense amplifier, space efficiency can be highly improved without damaging the operating characteristics of a dynamic random access memory.
Inventors
- 👤 Michihiro Inoue
- 👤 Toshio Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
153 words
A dynamic random access memory for writing information into memory devices connected to bit lines and for reading out information therefrom, comprising: bit lines and word lines; plural memory arrays disposed in an open bit memory array composition having memory devices disposed at all intersections of said bit lines and word lines; a sense amplifier row composed of a plurality of sense amplifiers disposed among said plural memory arrays, said plurality of sense amplifiers composing the sense amplifier row being arranged at a pitch which is double that of the pitch of said bit lines; wherein one of two pairs of it line pairs of said sense amplifier row which are arranged so as to be opposite to each other across a sense amplifier is connected to the sense amplifier, while bit lines isolated from the same sense amplifier are connected to two sense amplifiers which are adjacent to the same sense amplifier.
Claim 2
Dependent Claim
153 words
A dynamic random access memory for writing information into memory devices connected to bit lines and for reading out information therefrom, comprising: bit lines and word lines; plural memory arrays disposed in an open bit memory array composition having memory devices disposed at all intersections of said bit lines and word lines; a sense amplifier row composed of a plurality of sense amplifiers disposed among said plural memory arrays, said plurality of sense amplifiers composing the sense amplifier row being arranged at a pitch which is double that of the pitch of said bit lines; wherein one of two pairs of it line pairs of said sense amplifier row which are arranged so as to be opposite to each other across a sense amplifier is connected to the sense amplifier, while bit lines isolated from the same sense amplifier are connected to two sense amplifiers which are adjacent to the same sense amplifier.
Claim 3
Dependent Claim
147 words
A dynamic random access memory for writing information into memory devices connected to bit lines and for reading out information therefrom, comprising: bit lines and word lines; plural memory arrays disposed in an open bit memory array composition having memory devices disposed at all intersections of said bit lines and word lines; a sense amplifier row composed of a plurality of sense amplifiers disposed among said plural memory arrays, said plurality of sense amplifiers composing the sense amplifier row being arranged at a pitch which is double that of the pitch of said bit lines; wherein two bit lines at diagonally opposite positions across a sense amplifier out of four bit lines disposed within one sense amplifier pitch are connected to the sense amplifier, while bit lines isolated from the same sense amplifier are connected to two sense amplifiers which are adjacent to the same sense amplifier.
Claim 4
Dependent Claim
147 words
A dynamic random access memory for writing information into memory devices connected to bit lines and for reading out information therefrom, comprising: bit lines and word lines; plural memory arrays disposed in an open bit memory array composition having memory devices disposed at all intersections of said bit lines and word lines; a sense amplifier row composed of a plurality of sense amplifiers disposed among said plural memory arrays, said plurality of sense amplifiers composing the sense amplifier row being arranged at a pitch which is double that of the pitch of said bit lines; wherein two bit lines at diagonally opposite positions across a sense amplifier out of four bit lines disposed within one sense amplifier pitch are connected to the sense amplifier, while bit lines isolated from the same sense amplifier are connected to two sense amplifiers which are adjacent to the same sense amplifier.
References Cited (Backward Citations)
US3402398A
Cited
US4025907A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |