Interlaced memory matrix array having single transistor cells

Claim 1

A memory array comprising: a plurality of single transistor dynamic memory cells; a plurality of pairs of column conductors, each pair including an odd column conductor and an even column conductor; a plurality of differential sense amplifiers each coupled between an odd column conductor and an even column conductor of one of said plurality of pairs of column conductors; and a plurality of row conductors; said array of transistor cells being arranged in rows and columns such that each cell in an odd row is coupled to a corresponding row conductor and to the odd column conductor of the corresponding pair of column conductors and each cell of an even row is coupled to the corresponding row conductor and to the even column conductor of the corresponding pair of column conductors; each of said differential amplifiers providing to its respective pair of column conductors an inherent differential balance such that signals of very small amplitude can be detected from one or the other of said pair of column conductors according to whether an odd or even row cell is being accessed.