US3771148A
Expired / Lapsed
US
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Nonvolatile capacitive memory cell
Assignee: NCR Voyix Corp
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Filing: 1972-03-31
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Granted: 1973-11-06
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Expires: 1992-03-31
Abstract
Abstract The present invention relates to a nonvolatile capacitive memory cell, which has a capacitive means and a nonvolatile alterable threshold field effect transistor therein. The nonvolatile alterable threshold field effect transistor is used to capacitively store information in said capacitive means while power is applied to the nonvolatile capacitive memory cell. The nonvolatile alterable threshold field effect transistor is also used to nonvolatilely store a binary bit of information which is capacitively stored within the capacitive means, when power is lost to the nonvolatile capacitive memory cell. A pulse from a storage driver connected to the gate electrode of the nonvolatile alterable threshold field effect transistor causes the nonvolatile storage of said binary bit of information. When a binary one bit of information is capacitively stored in the volatile capacitive means, and power is lost, the threshold voltage of the nonvolatile alterable threshold field effect transistor will not be changed, representing the nonvolatile storage of a one bit by said transistor. When a binary zero bit of information is capacitively stored in the volatile capacitive means and power is lost, the threshold voltage of the nonvolatile alterable threshold field effect transistor will be changed, representing the nonvolatile storage of a zero bit by said transistor. A write data circuit is connected to the source electrode of the nonvolatile alterable threshold field effect transistor to capacitively store a binary bit of information into the capacitive means. A preset circuit and a storage circuit are used in nonvolatilely storing the one or zero bit of binary information of the capacitive means into the nonvolatile alterable threshold field effect transistor as power is lost to the nonvolatile capacitive memory cell.
Inventors
- 👤 N Aneshansley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C14/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
103 words
A nonvolatile capacitive memory cell for storing binary information therein, comprising: a. an alterable threshold field effect transistor capable of storing a charge in a nonvolatile manner, and having source and drain regions and a gate electrode comprising a layer of a first dielectric material disposed on a layer of a second dielectric material and forming an interface therebetween for storing information therein; b. capacitive means for storing infOrmation therein; and c. circuit means connecting the capacitive means to the drain region for transferring the information from the capacitive means to the interface of the dielectric layers for storage therein at power down.
Claim 2
Dependent Claim
103 words
A nonvolatile capacitive memory cell for storing binary information therein, comprising: a. an alterable threshold field effect transistor capable of storing a charge in a nonvolatile manner, and having source and drain regions and a gate electrode comprising a layer of a first dielectric material disposed on a layer of a second dielectric material and forming an interface therebetween for storing information therein; b. capacitive means for storing infOrmation therein; and c. circuit means connecting the capacitive means to the drain region for transferring the information from the capacitive means to the interface of the dielectric layers for storage therein at power down.
Claim 3
Dependent Claim
30 words
The nonvolatile capacitive memory cell of claim 1 and including refresh circuit means connectable to the gate electrode and source region for refreshing the the information in the capacitive means.
Claim 4
Dependent Claim
26 words
The nonvolatile capacitive memory cell of claim 2 wherein the refresh circuit means includes a differential amplifier and a switch connected in parallel with the amplifier.
Claim 5
Dependent Claim
39 words
The nonvolatile capacitive memory cell of claim 2 and including preset circuit means for presetting the alterable threshold field effect transistor prior to nonvolatilely storing the volatile information of the capacitive means in the interface of the gate electrode.
Claim 6
Dependent Claim
219 words
A nonvolatile capacitive memory cell for storing binary information therein comprising: a. semiconductor wafer; b. an alterable threshold field effect transistor, for nonvolatilely storing charge therein, built in the semiconductor wafer, the transistor having a source region, a drain region and a channel region, a source electrode and a drain electrode affixed to the source region and drain region respectively, an insulator layer structure comprising a layer of a first dielectric material disposed on the channel region, a layer of a second dielectric material disposed on the first layer and forming an interface which can nonvolatilely store information therein, a gate electrode to the second layer of the insulator layer structure; c. a capacitive means for storing information therein, having a first electrode comprising the conductive material of the wafer, a layer of a dielectric material disposed on, and in contact with, the first electrode, and a second electrode affixed to the layer of dielectric material; and d. a contact lead having one end in contact with the drain electrode of the alterable threshold field effect transistor and the other end in contact with the second electrode of the capacitive means to transfer the information capacitively stored in the capacitor means into the interface of the insulator layer structure of the alterable threshold field effect transistor at power down.
Claim 7
Dependent Claim
219 words
A nonvolatile capacitive memory cell for storing binary information therein comprising: a. semiconductor wafer; b. an alterable threshold field effect transistor, for nonvolatilely storing charge therein, built in the semiconductor wafer, the transistor having a source region, a drain region and a channel region, a source electrode and a drain electrode affixed to the source region and drain region respectively, an insulator layer structure comprising a layer of a first dielectric material disposed on the channel region, a layer of a second dielectric material disposed on the first layer and forming an interface which can nonvolatilely store information therein, a gate electrode to the second layer of the insulator layer structure; c. a capacitive means for storing information therein, having a first electrode comprising the conductive material of the wafer, a layer of a dielectric material disposed on, and in contact with, the first electrode, and a second electrode affixed to the layer of dielectric material; and d. a contact lead having one end in contact with the drain electrode of the alterable threshold field effect transistor and the other end in contact with the second electrode of the capacitive means to transfer the information capacitively stored in the capacitor means into the interface of the insulator layer structure of the alterable threshold field effect transistor at power down.
Claim 8
Dependent Claim
234 words
A nonvolatile capacitive memory cell circuit for storing binary information therein, comprising: a. alterable threshold field effect tranistor, for nonvolatilely storing information therein, built in a semiconductor substrate which has a source region and a drain region in the semiconductor substrate with a channel region therebetween, a source electrode and a drain electrode in contact with the source region and drain region respectively, an insulator layer structure which can nonvolatilely hold information therein in contact with said channel region, and a gate electrode in contact with said insulator layer structure; b. a capacitive means for capacitively storing information therein, having a first electrode comprising conductive material of the substrate, a layer of a dielectric material disposed on and, in contact with said first electrode, and a second electrode disposed on and in contact with the layer of dielectric material; c. a contact lead having one end in contact with said drain electrode of said alterable threshold field effect transistor and the other end in contact with the second electrode of said dielectric capacitor to transfer information capacitively stored in the capacitive means into the alterable threshold field effect transistor at power down; and d. a storage circuit means connectable to the gate electrode of the alterable threshold field effect transistor for causing the nonvolatilely storing any capacitively stored information of the capacitive means in the alterable threshold field effect transistor via the contact lead.
Claim 9
Dependent Claim
234 words
A nonvolatile capacitive memory cell circuit for storing binary information therein, comprising: a. alterable threshold field effect tranistor, for nonvolatilely storing information therein, built in a semiconductor substrate which has a source region and a drain region in the semiconductor substrate with a channel region therebetween, a source electrode and a drain electrode in contact with the source region and drain region respectively, an insulator layer structure which can nonvolatilely hold information therein in contact with said channel region, and a gate electrode in contact with said insulator layer structure; b. a capacitive means for capacitively storing information therein, having a first electrode comprising conductive material of the substrate, a layer of a dielectric material disposed on and, in contact with said first electrode, and a second electrode disposed on and in contact with the layer of dielectric material; c. a contact lead having one end in contact with said drain electrode of said alterable threshold field effect transistor and the other end in contact with the second electrode of said dielectric capacitor to transfer information capacitively stored in the capacitive means into the alterable threshold field effect transistor at power down; and d. a storage circuit means connectable to the gate electrode of the alterable threshold field effect transistor for causing the nonvolatilely storing any capacitively stored information of the capacitive means in the alterable threshold field effect transistor via the contact lead.
Claim 10
Dependent Claim
36 words
The nonvolatile capacitive memory cell circuit of claim 6 and further including refresh circuIt means connectable to the source electrode of the alterable threshold field effect transistor for refreshing the information stored in said capacitive means.
Claim 11
Dependent Claim
27 words
The nonvolatile capacitive memory cell circuit of claim 7 wherein the refresh circuit means includes a differential amplifier and a switch connected in parallel with the amplifier.
Claim 12
Dependent Claim
39 words
The nonvolatile capacitive memory cell circuit of claim 7, also including a preset circuit means connectable to the gate electrode of the alterable threshold field effect transistor for presetting the threshold voltage of the alterable threshold field effect transistor.
Claim 13
Dependent Claim
308 words
An array of nonvolatile capacitive memory cells for storing several binary bits of binary information therein, comprising: a. a plurality of address lines; b. a plurality of read, write and refresh lines; c. a plurality of groups of alterable threshold field effect transistors built in a semiconductor substrate, each alterable threshold field effect transistor having a source region, a drain region and a channel region therebetween, a source electrode and a drain electrode in contact with the source region and drain region respectively, an insulator layer structure disposed on and in contact with said channel region, and comprising a first layer of a first dielectric material disposed on the channel region and a second layer of a second dielectric material disposed on the first layer and forming an interface between the two layers suitable for storage of information therein and a gate electrode in contact with said insulator layer structure, each transistor in each group of transistors has its gate electrode connected to its respective address line and its source electrode connected to its own different one of the plurality of read, write and refresh line; d. a plurality of capacitive means to capacitively store several bits of information therein, each capacitive means have a first electrode comprising conductive material of the substrate, a layer of a dielectric disposed on and in contact with said first conductive material, and a second electrode disposed on and in contact with the layer of dielectric material; and e. a plurality of contact leads, each contact lead having one end in contact with a drain electrode of an alterable threshold field effect transistor and the other end in contact with the first electrode of a capacitive means to form a nonvolatile memory cell for nonvolatile storage of information which is transferred to the connected alterable threshold field effect transistor at power down.
Claim 14
Dependent Claim
308 words
An array of nonvolatile capacitive memory cells for storing several binary bits of binary information therein, comprising: a. a plurality of address lines; b. a plurality of read, write and refresh lines; c. a plurality of groups of alterable threshold field effect transistors built in a semiconductor substrate, each alterable threshold field effect transistor having a source region, a drain region and a channel region therebetween, a source electrode and a drain electrode in contact with the source region and drain region respectively, an insulator layer structure disposed on and in contact with said channel region, and comprising a first layer of a first dielectric material disposed on the channel region and a second layer of a second dielectric material disposed on the first layer and forming an interface between the two layers suitable for storage of information therein and a gate electrode in contact with said insulator layer structure, each transistor in each group of transistors has its gate electrode connected to its respective address line and its source electrode connected to its own different one of the plurality of read, write and refresh line; d. a plurality of capacitive means to capacitively store several bits of information therein, each capacitive means have a first electrode comprising conductive material of the substrate, a layer of a dielectric disposed on and in contact with said first conductive material, and a second electrode disposed on and in contact with the layer of dielectric material; and e. a plurality of contact leads, each contact lead having one end in contact with a drain electrode of an alterable threshold field effect transistor and the other end in contact with the first electrode of a capacitive means to form a nonvolatile memory cell for nonvolatile storage of information which is transferred to the connected alterable threshold field effect transistor at power down.
Claim 15
Dependent Claim
32 words
The array of nonvolatile capacitive memory cells of claim 10, also including a refresh circuit means connected to each of the plurality of transistors for refreshing the information in each memory cell.
Claim 16
Dependent Claim
40 words
The array of nonvolatile capacitive memory cells of claim 11 wherein: the refresh circuit means includes a differential amplifier and a switch connected in parallel with the amplifier connected into each of the plurality of read, write and refresh lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-05 | 1977-05-07 | 1977-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-05 | 1981-05-07 | 1981-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-05 | 1985-05-07 | 1985-11-06 | $7700.00 | Window Closed / Lapsed |