Semiconductor memory device having a divided bit line structure

Claim 2

A semiconductor memory deice having data input/output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of divided bit line pairs connecting the memory cells, said divided bit line pairs extending along a given column of memory cells; a pair of main bit lines extending substantially parallel to the divided bit line pairs and connected to data input/output lines; a plurality of sense amplifiers, each producing an output signal at an output terminal, one of said sense amplifiers being arranged between each two adjacent divided bit line pairs; a plurality of first switching means, each being provided for connecting one of the sense amplifiers to a selected one of the two adjacent divided bit line paris; and a plurality of second switching means for transferring the output signal of each of said sense amplifiers to said pair of main bit lines after said first switching means connects said sense amplifier to said selected one of the two adjacent divided bit line paris.

Claim 3

A semiconductor memory device according to claim 1, in which each of said second switching means is arranged between a respective one of said divided bit line paris and said main bit line pair.

Claim 4

A semiconductor memory device according to claim 1, in which each of said second switching means is arranged between the output terminal of a respective one of said sense amplifiers and said main bit line pair.

Claim 5

A semiconductor memory device having data input/output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of first divided bit line pairs extending along an Nth column of memory cells, and connected to the memory cells of the Nth column; a first pair of main bit lines including first and second main bit lines, extending substantially parallel to said first divided bit line paris, and connected to data input/output lines; a plurality of first sense amplifiers, each producing an output signal at an output terminal, one f said first sense amplifiers being provided for each of said first divided bit line paris; a plurality of first switch means for transferring the output signal of each of said first sense amplifiers to said first pair of main bit lines; a plurality of second divided bit line paris extending along an (N+1)th column of memory cells, and connected to the memory cells of the (N+1)th column; a second pair of main bit lines including said second main bit line and a third main bit line, extending substantially parallel to said second divided bit line paris, and connected to said data input/output lines; a plurality of second sense amplifiers, each producing an output signal at an output terminal, one of said second sense amplifiers being provided for one of said second divided bit line paris; and a plurality of second switch means for transferring the output signal of each of said second sense amplifier to said second pair of main bit lines.

Claim 6

A semiconductor memory device having data input/output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of first divided bit line pairs extending along an Nth column of memory cells, and connected to the memory cells of the Nth column; a first pair of main bit lines including first and second main bit lines, extending substantially parallel to said first divided bit line paris, and connected to data input/output lines; a plurality of first sense amplifiers, each producing an output signal at an output terminal, one f said first sense amplifiers being provided for each of said first divided bit line paris; a plurality of first switch means for transferring the output signal of each of said first sense amplifiers to said first pair of main bit lines; a plurality of second divided bit line paris extending along an (N+1)th column of memory cells, and connected to the memory cells of the (N+1)th column; a second pair of main bit lines including said second main bit line and a third main bit line, extending substantially parallel to said second divided bit line paris, and connected to said data input/output lines; a plurality of second sense amplifiers, each producing an output signal at an output terminal, one of said second sense amplifiers being provided for one of said second divided bit line paris; and a plurality of second switch means for transferring the output signal of each of said second sense amplifier to said second pair of main bit lines.

Claim 7

A semiconductor device having data input/ output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of first divided bit line paris extending along an Nth column of said memory cells, and connected to the memory cells of the Nth column; a plurality of second divided bit line pairs extending along an (N+1)th column of said memory cells, and connected to said memory cells of the (N+1)th column; a pair of main bit lines having first and second main bit lines, being arranged between said first divided bit line paris and said second divided bit line paris, extending substantially parallel to said first divided bit line paris and to said second divided bit line paris, and connected to said data input/output lines; a plurality of first sense amplifiers, each producing an output signal at an output terminal, one of said first sense amplifiers being provided for each of said first divided bit line paris; a plurality of first switch means for transferring the output signal of each of said first sense amplifiers to said pair of main bit lines; a plurality of second sense amplifiers, each producing an output signal at an output terminal, one of said second sense amplifiers being provided for one of said second divided bit line paris; and a plurality of second switch means for transferring the output signal of each of said second sense amplifiers to said pair of main bit lines.

Claim 8

A semiconductor device having data input/ output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of first divided bit line paris extending along an Nth column of said memory cells, and connected to the memory cells of the Nth column; a plurality of second divided bit line pairs extending along an (N+1)th column of said memory cells, and connected to said memory cells of the (N+1)th column; a pair of main bit lines having first and second main bit lines, being arranged between said first divided bit line paris and said second divided bit line paris, extending substantially parallel to said first divided bit line paris and to said second divided bit line paris, and connected to said data input/output lines; a plurality of first sense amplifiers, each producing an output signal at an output terminal, one of said first sense amplifiers being provided for each of said first divided bit line paris; a plurality of first switch means for transferring the output signal of each of said first sense amplifiers to said pair of main bit lines; a plurality of second sense amplifiers, each producing an output signal at an output terminal, one of said second sense amplifiers being provided for one of said second divided bit line paris; and a plurality of second switch means for transferring the output signal of each of said second sense amplifiers to said pair of main bit lines.

Claim 9

A semiconductor memory device having data input/output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of divided bit line paris connecting the memory cells, said divided bit line paris extending along a given column of memory cells; first and second main bit line paris extending substantially parallel to the divided bit line paris and connected to data input/output lines; a plurality of sense amplifiers, each producing an output signal at an output terminal, and one of said sense amplifiers being provided for each of said divided bit line paris; a plurality of first switching means for transferring the output signal of each of said sense amplifiers to said first main bit line pair; and a plurality of second switching means for transferring the output signal of each of said sense amplifiers to said second main bit line pair.

Claim 10

A semiconductor memory device having data input/output lines, comprising: an array of memory cells arranged in rows and columns; a plurality of divided bit line paris connecting the memory cells, said divided bit line paris extending along a given column of memory cells; first and second main bit line paris extending substantially parallel to the divided bit line paris and connected to data input/output lines; a plurality of sense amplifiers, each producing an output signal at an output terminal, and one of said sense amplifiers being provided for each of said divided bit line paris; a plurality of first switching means for transferring the output signal of each of said sense amplifiers to said first main bit line pair; and a plurality of second switching means for transferring the output signal of each of said sense amplifiers to said second main bit line pair.