US4777625A
Expired / Lapsed
US
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Divided-bit line type dynamic semiconductor memory with main and sub-sense amplifiers
Assignee: Toshiba Corp
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Filing: 1987-08-26
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Granted: 1988-10-11
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Expires: 2007-08-26
Abstract
Abstract There is disclosed a divided-bit line type dynamic random access memory having parallel main bit line pairs which are formed on a substrate and to each of which sub-bit line pairs are provided in parallel with each other. Parallel word lines insulatively cross the sub-bit line pairs. Memory cells are provided at the crossing points of the sub-bit line pairs and the word lines. Each memory cell has a capacitor for storing information and a voltage-controlled switching transistor such as a MOSFET. First sense amplifier circuits are connected to the sub-bit line pairs, while second sense amplifier circuits are connected to the main bit line pairs. In a restoring mode, a specific sub-bit line pair, to which a selected memory cell is connected, is electrically disconnected from the corresponding main bit one pair, and a first sense amplifier circuit connected thereto is activated to perform a restoring operation. At this time, the remaining sub-bit line pairs other than the specific sub-bit line pair are also connected to the corresponding main bit line pair, and the first sense amplifier circuits of the remaining sub-bit line pairs are rendered inoperative to save power consumption.
Inventors
- 👤 Koji Sakui
- 👤 Shigeyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C11/4091
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
249 words
A divided-bit line type dynamic random access memory comprising: (a) parallel main bit line pairs formed on a substrate, said main bit line pairs including a certain main bit line pair; (b) aub-bit line pairs provided in said certain main bit line pair; (c) transfer gate means connected between each of said sub-bit line pairs and said certain main bit line pair, for performing a switching operation in such a manner as to selectively control the electrical connection between said sub-bit line pairs and said certain main bit line pair; (d) parallel word lines provided on said substrate to insulatively cross with said sub-bit pairs; (e) memory cells provided at crossing points of said sub-bit line pairs and said word lines, each of said memory cells having a capacitive element for storing information and a switching transistor; (f) first sense amplifier means connected to said main bit line pairs, for sensing and amplifying a potential difference on said certain main bit line pair connected to said specific sub-bit line pair, said first sense amplifier means comprising differential amplifier circuits; and (g) second sense amplifier means connected to said sub-bit line pairs, for sensing, in a data restoring mode, information stored in a selected memory cell which appears as a potential difference on a specific sub-bit line pair to which said selected memory cell is connected and which is disconnected from said certain main bit line pair, said second sense amplifier means comprising flip-flop amplifier circuits formed using unipolar transistors.
Claim 2
Dependent Claim
249 words
A divided-bit line type dynamic random access memory comprising: (a) parallel main bit line pairs formed on a substrate, said main bit line pairs including a certain main bit line pair; (b) aub-bit line pairs provided in said certain main bit line pair; (c) transfer gate means connected between each of said sub-bit line pairs and said certain main bit line pair, for performing a switching operation in such a manner as to selectively control the electrical connection between said sub-bit line pairs and said certain main bit line pair; (d) parallel word lines provided on said substrate to insulatively cross with said sub-bit pairs; (e) memory cells provided at crossing points of said sub-bit line pairs and said word lines, each of said memory cells having a capacitive element for storing information and a switching transistor; (f) first sense amplifier means connected to said main bit line pairs, for sensing and amplifying a potential difference on said certain main bit line pair connected to said specific sub-bit line pair, said first sense amplifier means comprising differential amplifier circuits; and (g) second sense amplifier means connected to said sub-bit line pairs, for sensing, in a data restoring mode, information stored in a selected memory cell which appears as a potential difference on a specific sub-bit line pair to which said selected memory cell is connected and which is disconnected from said certain main bit line pair, said second sense amplifier means comprising flip-flop amplifier circuits formed using unipolar transistors.
Claim 3
Dependent Claim
30 words
The device according to claim 1, wherein said second sense amplifier circuits comprise a current mirror type differential amplifier having a BIMOS structure constituted by unipolar transistors and bipolar transistors.
Claim 4
Dependent Claim
109 words
The memory according to claim 1, wherein said transfer gate means electrically connects said sub-bit line pairs to said certain main bit line pair in a precharge mode and the data readout mode, and, in a restoring mode, electrically disconnects said specific sub-bit line pair from said certain main bit line pair and activates a second sense amplifier circuit connected to said specific sub-bit line pair, thereby performing a restoring operation on said specific sub-bit line pair, with those second sense amplifier circuits which are connected to remaining sub-bit line pairs provided on said certain main bit line pair other than said specific sub-bit line pair being rendered inoperative.
Claim 5
Dependent Claim
40 words
The memory according to claim 1, wherein said differential amplifier circuits comprise current-mirror type differential amplifiers in each of which said unipolar transistors constitute a source follower circuit connected between said certain main bit line pair and said bipolar transistors.
Claim 6
Dependent Claim
17 words
The memory according to claim 4, wherein said unipolar transistors include metal oxide semiconductor field effect transistors.
Claim 7
Dependent Claim
60 words
The memory according to claim 1, further comprising: (h) parallel dummy word lines formed on said substrate to insulatively cross said main bit line pairs; and (i) dummy cells provided at crossing points of said main bit line pairs and said dummy word lines, each of said dummy cells having a capacitive element for storing information and a voltage-controlled transistor.
Claim 8
Dependent Claim
33 words
The device according to claim 6, wherein said capacitive element of each of said dummy cells has a capacitance substantially half of that of said capacitive element of each of said memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-11 | 1992-04-11 | 1992-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-11 | 1996-04-11 | 1996-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-11 | 2000-04-11 | 2000-10-11 | $7700.00 | Window Closed / Lapsed |