US4628486A
Expired / Lapsed
US
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MOS dynamic random access memory
Assignee: Toshiba Corp
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Filing: 1984-12-13
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Granted: 1986-12-09
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Expires: 2004-12-13
Abstract
Abstract In a MOS-dRAM formed by integrating memory cells each formed of an MOS capacitor and an MOSFET, a D-type transistor with a threshold voltage lower than that of MOSFETs of peripheral circuits is used for the MOSFET of each memory cell. Thus, a word line driver without a pull-up circuit can be used, permitting high-speed access of the MOS-dRAM.
Inventors
- 👤 Koji Sakui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4085
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
190 words
A MOS-dynamic random access memory, comprising: a semiconductor substrate; a memory array formed of a plurality of memory cells arranged in a matrix on the substrate, each of said memory cells including a memory capacitor and a switching MOSFET having a gate, a source, a drain, and a channel region doped with impurities of a conductivity type opposite to that of the substrate; a plurality of word lines formed on the substrate each connected in common with the gates of the switching MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array; a decoder formed on the substrate for selectively driving said plurality of word lines, including an output MOSFET and a flip-flop connected to the source of the output MOSFET, wherein a substrate bias voltage delivered from a back-gate bias circuit is used as a reference potential of said flip-flop; a clock generator formed on the substrate for controlling the operating timing of the decoder; and a level shift circuit formed on the substrate connected between an output of said clock generator and the drain of the output MOSFET of said decoder.
Claim 2
Dependent Claim
190 words
A MOS-dynamic random access memory, comprising: a semiconductor substrate; a memory array formed of a plurality of memory cells arranged in a matrix on the substrate, each of said memory cells including a memory capacitor and a switching MOSFET having a gate, a source, a drain, and a channel region doped with impurities of a conductivity type opposite to that of the substrate; a plurality of word lines formed on the substrate each connected in common with the gates of the switching MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array; a decoder formed on the substrate for selectively driving said plurality of word lines, including an output MOSFET and a flip-flop connected to the source of the output MOSFET, wherein a substrate bias voltage delivered from a back-gate bias circuit is used as a reference potential of said flip-flop; a clock generator formed on the substrate for controlling the operating timing of the decoder; and a level shift circuit formed on the substrate connected between an output of said clock generator and the drain of the output MOSFET of said decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |