High-speed refreshing rechnique for highly-integrated random-access memory

Claim 2

A dynamic semiconductor memory device having a substrate, said device comprising: (a) parallel main bit line pairs formed on the substrate, said main bit line pairs including a certain main bit line pair; (b) sub-bit line pairs connected to said certain main bit line pair; (c) parallel word lines provided on the substrate to insulatively cross respective of said sub-bit line pairs; (d) memory cells for capacitively storing information, said memory cells being connected to crossing points of said sub-bit line pairs and said work lines; (e) first sense amplifier circuits respectively connected to said sub-bit line pairs; (f) second sense amplifier circuits respectively connected to said main bit line pairs; and (g) control means, connected to said sub-bit line pairs and said first sense amplifier circuits, for, when a refreshing operation is executed in a refreshing mode of said memory device, selecting simultaneously a plurality of word lines which are associated with different sub-bit lines, for activating said first sense amplifier circuits, and for refreshing together memory cells which are connected to the word lines thus selected.

Claim 3

The device according to claim 1, wherein said control means selects, at the same time, the same number of word lines as that of said sub-bit line pairs, each of the selected word lines being connected to a memory cell included in one corresponding sub-bit line pair and being subjected to the refreshing operation together with other memory cells thus selected simultaneously.

Claim 4

The device according to claim 2, wherein said control means comprises: transfer gate means connected between said sub-bit line pairs and said main bit line pairs, for being voltage-controlled to perform a switching operation, thereby electrically disconnecting said sub-bit line pairs from said certain main bit line pair, during the same number of word lines as that of said sub-bit line pairs are selected simultaneously.

Claim 5

The device according to claim 2, wherein, even in a reading/writing mode of said memory device, said control means selects, for a single data restoring operation, the same number of word lines as that of said sub-bit line pairs including a word line which is connected to a memory cell under accessing, whereby memory cells connected to the selected word lines are subjected simultaneously to the data rewriting operation.

Claim 6

The device according to claim 3, wherein said control means selects, in a reading/writing mode of said memory device, a specific word line connected to a memory cell under accessing, which cell is then subjected to a data rewriting operation.

Claim 7

The device according to claim 3, wherein said transfer gate means comprises unipolar transistors.

Claim 8

The device according to claim 3, wherein said control means activates simultaneously said first sense amplifier circuits during said same number of word lines as that of said sub-bit line pairs are selected simultaneously.

Claim 9

The device according to claim 3, wherein said control means activates sequentially said first sense amplifier circuits during said same number of word lines as that of said sub-bit line pairs are selected simultaneously.

Claim 10

The device according to claim 3, wherein said memory device is a random-access memory.

Claim 11

A dynamic random-access memory of divided-bit line type, said memory comprising: (a) a fiirst number of pairs of main bit lines; (b) main sense amplifiers connected respectively to said pairs of main bit lines; (c) a second number of pairs of sub-bit lines which are connected to each of said pairs of main bit lines through transfer gates for performing a switching operation; (d) a third number of word lines divided into the same number of sections as said second number, each of which sections consists of a fourth number of word lines insulatively crossing one pair of said sub-bit lines; (e) memory cells provided at crossing points of said sub-bit lines and said third number of word lines; (f) sub-sense amplifiers connected respectively to said second number of pairs of sub-bit lines; and (g) refreshing controller means, connected to said transfer gates, said third number of word lines and said sub-sense amplifiers, for simultaneously activating in a refreshing mode of said memory, a predetermined number of word lines which are selected by respectively designating a word line from every one of said second number of sections, said predetermined number being the same as said second number, and for making said sub-sense amplifiers active to simultaneously refresh memory cells which are included in said second number of pairs of sub-bit lines in each of said pairs of main bit lines and which are connected to said predetermined number of word lines thus selected.

Claim 12

A dynamic random-access memory of divided-bit line type, said memory comprising: (a) a fiirst number of pairs of main bit lines; (b) main sense amplifiers connected respectively to said pairs of main bit lines; (c) a second number of pairs of sub-bit lines which are connected to each of said pairs of main bit lines through transfer gates for performing a switching operation; (d) a third number of word lines divided into the same number of sections as said second number, each of which sections consists of a fourth number of word lines insulatively crossing one pair of said sub-bit lines; (e) memory cells provided at crossing points of said sub-bit lines and said third number of word lines; (f) sub-sense amplifiers connected respectively to said second number of pairs of sub-bit lines; and (g) refreshing controller means, connected to said transfer gates, said third number of word lines and said sub-sense amplifiers, for simultaneously activating in a refreshing mode of said memory, a predetermined number of word lines which are selected by respectively designating a word line from every one of said second number of sections, said predetermined number being the same as said second number, and for making said sub-sense amplifiers active to simultaneously refresh memory cells which are included in said second number of pairs of sub-bit lines in each of said pairs of main bit lines and which are connected to said predetermined number of word lines thus selected.

Claim 13

The memory according to claim 10, wherein said refreshing controller means comprises: a row address decoder circuit provided on a substrate of said memory to have drivers having the same number as said second number, each of which is connected in common to correponding word lines respectively included in said second number of sections.

Claim 14

The memory according to claim 11, wherein said decoder circuit is formed on a substrate of said memory.