EP0101884A2
Expired / Lapsed
EP
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Monolithic semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1983-07-19
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Granted: —
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Expires: 2003-07-19
Abstract
Abstract A semiconductor memory having data lines (D oo - D 13 ) divided lengthwise, which data lines cross word lines (W) in a memory cell array and selectively coupled to memory cells (MC) is disclosed. A plurality of second data lines I/0(0), 1/0(1) are arranged one for each of predetermined groups of the data lines to exchange data through first switches (SW oo -SW 13 ), and one or more third data lines (I/O) are arranged orthogonally to the second data lines to exchange data with the second data lines through second switches (SW YO , SW Y1 ). Read/write controllers (RWC) are coupled to the third data lines. Data are read and written for desired memory cells by selective drive of the word lines and the first and second switches.
Inventors
- 👤 Kiyoo Itoh
- 👤 Ryoichi Hori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/18; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/06; G11C5/063; G11C7/10; G11C7/1006; H; H10; H10D; H10D99/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
188 words
A monolithic semiconductor memory comprising: a plurality of word lines (W) adapted to be selectively driven by an address signal; a plurality of first data lines (D O1 . D 02' D 03' D 04' D 10' D 11' D 12' D 13 ) each arranged to cross said word lines and divided lengthwise; a plurality of memory cells (MC) each arranged at each of crosspoints of said word lines and said first data lines and adapted to be coupled to a corresponding one of said first data lines when a corresponding one of said word lines is driven; a plurality of second data lines (i/o(0) i/o(l) .....) each arranged for each of predetermined groups of said first data lines for exchanging data with selected ones of said first data lines through first switching means (SW 00 - SW 13) ; a one or more third data lines (I/O) arranged orthogonally to said second data lines for exchanging data with selected ones of said second data lines through second switching means (SW Y0 , SW Y1 ); and read/write control means (RWC) associated with said third data lines.
Claim 2
Dependent Claim
188 words
A monolithic semiconductor memory comprising: a plurality of word lines (W) adapted to be selectively driven by an address signal; a plurality of first data lines (D O1 . D 02' D 03' D 04' D 10' D 11' D 12' D 13 ) each arranged to cross said word lines and divided lengthwise; a plurality of memory cells (MC) each arranged at each of crosspoints of said word lines and said first data lines and adapted to be coupled to a corresponding one of said first data lines when a corresponding one of said word lines is driven; a plurality of second data lines (i/o(0) i/o(l) .....) each arranged for each of predetermined groups of said first data lines for exchanging data with selected ones of said first data lines through first switching means (SW 00 - SW 13) ; a one or more third data lines (I/O) arranged orthogonally to said second data lines for exchanging data with selected ones of said second data lines through second switching means (SW Y0 , SW Y1 ); and read/write control means (RWC) associated with said third data lines.
Claim 3
Dependent Claim
33 words
A monolithic semiconductor memory-according to Claim 1 wherein sense amplifiers (SA 1 , SA 2 , SA 3 ) are connected to any or all of said first, second and third data lines.
Claim 4
Dependent Claim
18 words
A monolithic semiconductor memory according to Claim 1 wherein said first, second and third data lines are paired.
Claim 5
Dependent Claim
29 words
A monolithic semiconductor memory according to Claim 3 wherein differential sense amplifiers (S A ) are connected to any or all of said first, second and third data lines.
Claim 6
Dependent Claim
22 words
A monolithic semiconductor memory according to Claim 1 wherein said second data lines are arranged in parallel to said first data lines.
Claim 7
Dependent Claim
29 words
A monolithic semiconductor memory according to Claim 5 wherein control lines (201- 204) carrying signals to control said first switching means are arranged orthogonally to said first data lines.
Claim 8
Dependent Claim
21 words
A monolithic semiconductor memory according to Claim 1 wherein said second data lines are arranged orthogonally to said first data lines.
Claim 9
Dependent Claim
31 words
A monolithic semiconductor memory according to Claim 7 wherein control lines (401 - 404) carrying signals to control said first switching means are arranged in parallel to said first data lines.
Claim 10
Dependent Claim
52 words
A monolithic semiconductor memory according to Claim 7 wherein said second data lines are provided one for each of predetermined groups of parallelly arranged ones of said first data lines, and said third data lines are provided one for each of predetermined groups of parallelly arranged ones of said second data lines.
Claim 11
Dependent Claim
28 words
A monolithic semiconductor memory according to Claim 9 wherein said third data lines are connected to said read/write control means through third switching means (SW 2 ) .
References Cited (Backward Citations)
No citation records indexed.
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