Patent US5386556A successfully refreshed from Google Patents.
EP0258715A2
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Static random access memory having bi-cmos construction
Assignee: NEC Corp
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Filing: 1987-08-14
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Granted: —
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Expires: 2007-08-14
Abstract
Abstract A semiconductor memory of a Bi-CMOS construction is disclosed. The memory includes a plurality of cell blocks connected in common to a pair of main-bit lines. Each of the cell blocks includes a plurality of word lines, a pair of pre-bit lines, a plurality of memory cell each connected to one of the word lines and to the pre-bit lines, and a pair of bipolar transistors having the respective bases connected to the pre-bit lines and the respective collector-emitter current paths connected in series between the main-bit lines. One of the bipolar transistors is turned ON in response to data stored in a selected memory cell to discharge the associated main-bit line. The discharging of the pre-bit line and the main-bit line is thus carried out rapidly to increase data read operation speed.
Inventors
- 👤 Hiroshi C/O Nec Corporation Shiba
- 👤 Shoji C/O Nec Corporation Eguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 20:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C11/412; G11C11/417; G11C11/419; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
181 words
I. A semiconductor memory comprising a pair of main-bit lines; a plurality of cell blocks, each of said cell blocks including a plurality of word lines, a pair of pre-bit lines, a plurality of memory cells each connected to one of said word lines and to said pre-bit lines, a first node connected to one of said main-bit lines, a second node connected to the other of said main-bit lines, a third node, a first transistor of a bipolar type having a base connected to one of said pre-bit lines and a collector-emitter current path connected between said first and third nodes, a second transistor of said bipolar type having a base connected to the other of said pre-bit lines and a collector-emitter current path connected between said second and third nodes, and a third transistor connected between said third node and a reference point and means responsive to a set of address signals for selecting one of said word lines in one of said cell blocks and for turning on said third transistor in said one of said cell blocks.
Claim 2
Dependent Claim
32 words
The memory as claimed in claim I, wherein each of said memory cells includes fourth and fifth transistors of an insulated gate field effect type which are cross-coupled in a flip-flop form.
Claim 3
Dependent Claim
19 words
The memory as claimed in claim 2, wherein said third transistor is of said insulated gate field effect transistor.
Claim 4
Dependent Claim
16 words
The memory as claimed in claim 2, wherein said third transistor is of said bipolar type.
Claim 5
Dependent Claim
208 words
A semiconductor memory comprising at last one first line supplied with a first selection signal, a pair of second line, at least one memory cell connected to said at least one first line and said second lines, a pair of third lines, a circuit node, a reference terminal, a first transistor of a bipolar type having a base connected to one of said second lines, a collector connected to one of said third lines and an emitter connected to said circuit node, a second transistor of said bipolar type having a base connected to the other of said second lines, a collector connected to the other of said third lines and an emitter connected to said circuit node, a third transistor connected between said circuit node and said reference terminal and receiving a second selection signal, means for operatively amplifying a first potential difference between said third lines caused by conducting states of said third transistor and one of said first and second transistors to produce an output data signal, and means responsive to an input data signal for operatively producing a second potential difference between said third lines and transferring said second potential difference to said second lines via collector-base junctions of said first and second transistors.
Claim 6
Dependent Claim
30 words
The memory as claimed in claim 5, wherein said memory cell includes fourth and fifth transistors of an insulated gate field effect type which are cross-coupled in a flip-flop form.
Claim 7
Dependent Claim
19 words
The memory as claimed in claim 6, wherein said third transistor is of said insulated gate field effect type.
Claim 8
Dependent Claim
16 words
The memory as claimed in claim 6, wherein said third transistor is of said bipolar type.
Claim 9
Dependent Claim
136 words
A semiconductor memory comprising a plurality of word lines, a pair of pre-bit lines, a plurality of memory cells each connected to one of said word lines and to said pre-bit lines, a reference node, a pair of main-bit lines, a first bipolar transistor having a base connected to one of said pre-bit lines and a collector-emitter current path connected between one of said main-bit lines and said reference node, and a second bipolar transistor having a base connected to the other of said pre-bit lines and a collector-emitter current path connected between the other of said main-bit lines and said reference node, one of said first and second bipolar transistors being turned ON in response to data stored in a selected one of said memory cells to discharge the associated one of said maij-bit lines.
Claim 10
Dependent Claim
29 words
The memory as claimed in claim 9, wherein each of said memory cells includes first and second insulated gate field effect transistors which are cross-coupled in a flip-flop form.
References Cited (Backward Citations)
No citation records indexed.
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