US5657287A
Expired / Lapsed
US
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Enhanced multiple block writes to adjacent blocks of memory using a sequential counter
Assignee: Round Rock Research LLC
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Filing: 1995-05-31
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Granted: 1997-08-12
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Expires: 2015-05-31
Abstract
Abstract A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.
Inventors
- 👤 Loren L. McLaury
- 👤 Donald M. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1075; G11C8/00; G11C8/04; G11C8/12
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
64 words
An integrated circuit comprising: an array of randomly addressable registers, blocks of the randomly addressable registers being addressable by an address for writing data to a block of randomly addressable registers simultaneously; and a burst counter for incrementing the address when at least one individual block write is performed to address a next block of addressable registers of the array of randomly addressable registers.
Claim 2
Dependent Claim
64 words
An integrated circuit comprising: an array of randomly addressable registers, blocks of the randomly addressable registers being addressable by an address for writing data to a block of randomly addressable registers simultaneously; and a burst counter for incrementing the address when at least one individual block write is performed to address a next block of addressable registers of the array of randomly addressable registers.
Claim 3
Dependent Claim
48 words
The integrated circuit according to claim 1, further comprising control logic for initiating a plurality of functional modes, including a block write mode during which block writes are performed, the burst counter increments the address as a function of at least one of the plurality of functional modes.
Claim 4
Dependent Claim
42 words
The integrated circuit according to claim 1, wherein the burst counter sequentially increments the address by n, where n is the number of bits in a plane of the array written to a block during the at least one individual block write.
Claim 5
Dependent Claim
60 words
The integrated circuit according to claim 3, wherein a plurality of adjacent blocks of the randomly addressable registers are addressed such that individual block writes are sequentially performed during a plurality of block write cycles, the burst counter incrementing an address of each block of the plurality of adjacent blocks by n for each of the individual block writes performed.
Claim 6
Dependent Claim
66 words
The integrated circuit according to claim 2, wherein the array of randomly addressable registers are arranged in rows and columns, each of the randomly addressable registers is addressable by a row and a column address, and further wherein the burst counter increments the column address of a row as a function of at least one of the plurality of functional modes performed in a burst mode.
Claim 7
Dependent Claim
41 words
The integrated circuit according to claim 5, wherein the at least one of the plurality of functional modes is a read function mode, the burst counter incrementing the column address of a row by one to address the next addressable register.
Claim 8
Dependent Claim
59 words
The integrated circuit according to claim 5, wherein the at least one of the plurality of functional modes is the block write mode, the burst counter incrementing the column address of the row by n, n generally corresponding to n=2 x wherein x is a number of addresses ignored to create a block written during the block write mode.
Claim 9
Dependent Claim
15 words
The integrated circuit of claim 1, wherein the randomly addressable registers contain substantially identical data.
Claim 10
Independent Claim
62 words
A method of addressing, comprising the steps of: providing an array of randomly a addressable registers; addressing a block of the randomly addressable registers by an address to perform a block write; writing to the block randomly addressable registers simultaneously: and internally incrementing the address for addressing a next addressable register of the randomly addressable registers upon performance of the block write.
Claim 11
Independent Claim
62 words
A method of addressing, comprising the steps of: providing an array of randomly a addressable registers; addressing a block of the randomly addressable registers by an address to perform a block write; writing to the block randomly addressable registers simultaneously: and internally incrementing the address for addressing a next addressable register of the randomly addressable registers upon performance of the block write.
Claim 12
Dependent Claim
80 words
The method of addressing according to claim 8, wherein the method further comprises the step of selecting at least one of a plurality of functional modes for writing to or reading from the randomly addressable registers in a burst mode, the plurality of functional modes including at least a block write mode for performing the block write; and wherein the incrementing step includes the step of incrementing the address in a sequential manner as a function of the selected mode.
Claim 13
Dependent Claim
77 words
The method of addressing according to claim 10, wherein the providing step includes the step of providing the array of randomly addressable registers arranged in rows and columns; wherein the addressing step includes the step of addressing the block of randomly addressable registers by a row and a column address; and wherein the incrementing step includes the step of incrementing the column address of a row in a sequential manner as a function of the selected mode.
Claim 14
Dependent Claim
35 words
The method of addressing according to claim 10, wherein the selected mode is a read mode, the incrementing step including the step of incrementing the address by one to address a next randomly addressable register.
Claim 15
Dependent Claim
41 words
The memory device according to claim 9, wherein the incrementing step includes the step of incrementing the address by n, wherein n is the number of bits per plane of the array of randomly addressable registers written during the block write.
Claim 16
Dependent Claim
14 words
The method of claim 8, wherein the randomly addressable registers contain substantially identical data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |