Abstract A multiport DRAM having a DRAM cell array; a sequential access memory (SAM) for inputting data of a specific length to the DRAM cell array and transmitting that data to an external device; a SAM address counter for counting the addresses of the data in the SAM; a serial port connected to the SAM for transmitting the data in the SAM to an external device; a data transfer address counter, the contents of which is cleared by inputting an external reset signal and is counted up by inputting an overflow signal which is output from the SAM address counter; and a data transfer controller for outputting a data transfer status signal which indicates that data transmission is in progress when data of a specific length in the DRAM cell array designated by the input of the overflow signal by the data transfer address counter is transmitted to the SAM.
A multiport DRAM comprising: a DRAM cell array; a sequential access memory (SAM) for inputting data of a specific length to the DRAM cell array and transmitting that data to an external device; a SAM address counter for counting the addresses of the data in the SAM; a serial port connected to the SAM for transmitting the data in the SAM to an external device; a data transfer address counter, the contents of which is cleared by inputting an external reset signal and is counted up by inputting an overflow signal which is output from the SAM address counter; and a data transfer control unit for outputting a data transfer status signal which indicates that data transmission is in progress when overflow data corresponding to said overflow signal in the DRAM cell array designated by the data transfer address counter is transmitted to the SAM.
Claim 2
Dependent Claim
145 words
A multiport DRAM comprising: a DRAM cell array; a sequential access memory (SAM) for inputting data of a specific length to the DRAM cell array and transmitting that data to an external device; a SAM address counter for counting the addresses of the data in the SAM; a serial port connected to the SAM for transmitting the data in the SAM to an external device; a data transfer address counter, the contents of which is cleared by inputting an external reset signal and is counted up by inputting an overflow signal which is output from the SAM address counter; and a data transfer control unit for outputting a data transfer status signal which indicates that data transmission is in progress when overflow data corresponding to said overflow signal in the DRAM cell array designated by the data transfer address counter is transmitted to the SAM.
Claim 3
Dependent Claim
59 words
A multiport DRAM according to claim 1, further comprising a display starting address register for specifying a starting address for transmitting data of a specific length in the DRAM cell array to the SAM, wherein the data transfer address counter, loads the display starting address into the display initiating address register on further input of an external reset signal.
Claim 4
Dependent Claim
35 words
A multiport DRAM according to claim 1, wherein data of a specific length transmitted from the DRAM cell array to the SAM is equivalent to the data in a row of the DRAM cell array.