US5654933A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Equilibrated sam read transfer circuit
Assignee: Micron Technology Inc
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Filing: 1997-01-21
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Granted: 1997-08-05
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Expires: 2017-01-21
Abstract
Abstract A circuit and method are described for transferring data from a dynamic random access memory (DRAM) to a serial access memory (SAM). The SAM includes an equilibration circuit and a bias circuit for equilibrating the SAM to a predetermined potential prior to transferring data. Data is transferred to the SAM by creating a differential voltage on the SAM and using the differential to latch the state of the data in the SAM.
Inventors
- 👤 Loren L. McLaury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
211 words
An integrated memory circuit comprising: a plurality of dynamic memory cells; a plurality of static memory cells selectively coupled to the plurality of dynamic memory cells, each of the static memory cells having first and second nodes and comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor; the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and an equilibrate circuit directly connected to the plurality of static memory cells for equilibrating the plurality of static memory cells to a predetermined potential, the equilibrate circuit comprising a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal; the equilibrate circuit further comprising a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 2
Dependent Claim
211 words
An integrated memory circuit comprising: a plurality of dynamic memory cells; a plurality of static memory cells selectively coupled to the plurality of dynamic memory cells, each of the static memory cells having first and second nodes and comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor; the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and an equilibrate circuit directly connected to the plurality of static memory cells for equilibrating the plurality of static memory cells to a predetermined potential, the equilibrate circuit comprising a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal; the equilibrate circuit further comprising a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 3
Dependent Claim
220 words
An integrated memory circuit comprising: a plurality of dynamic memory cells; a digit line selectively coupled to the plurality of dynamic memory cells; sense amplifiers connected to the digit line; a static memory cell selectively coupled to the digit line, the static memory cell comprising first and second nodes; and an equilibrate circuit directly connected to the first and second nodes for equilibrating the static memory cell to a predetermined potential, the static memory cell comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and the equilibrate circuit comprising: a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal, and a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 4
Dependent Claim
220 words
An integrated memory circuit comprising: a plurality of dynamic memory cells; a digit line selectively coupled to the plurality of dynamic memory cells; sense amplifiers connected to the digit line; a static memory cell selectively coupled to the digit line, the static memory cell comprising first and second nodes; and an equilibrate circuit directly connected to the first and second nodes for equilibrating the static memory cell to a predetermined potential, the static memory cell comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and the equilibrate circuit comprising: a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal, and a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 5
Dependent Claim
234 words
A multi-port memory comprising: a dynamic random access memory (DRAM) having a plurality of dynamic memory cells selectively coupled to a digit line; a p-sense amplifier and an n-sense amplifier connected to the digit line; a serial access memory (SAM) having a plurality of static memory cells selectively coupled to the digit line, each of the static memory cells having first and second nodes and comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and an equilibrate circuit directly connected to the plurality of static memory cells for equilibrating the plurality of static memory cells to a predetermined potential, the equilibrate circuit comprising: a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal, and a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 6
Dependent Claim
234 words
A multi-port memory comprising: a dynamic random access memory (DRAM) having a plurality of dynamic memory cells selectively coupled to a digit line; a p-sense amplifier and an n-sense amplifier connected to the digit line; a serial access memory (SAM) having a plurality of static memory cells selectively coupled to the digit line, each of the static memory cells having first and second nodes and comprising: a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal; and an equilibrate circuit directly connected to the plurality of static memory cells for equilibrating the plurality of static memory cells to a predetermined potential, the equilibrate circuit comprising: a first equilibrate transistor having a drain connected to the first node, a source connected to the second node, and a gate connected to receive an equilibration signal, and a second equilibrate transistor having a drain connected to receive an equilibrate voltage, a source connected to the drain of the grounding transistor, and a gate connected to receive the equilibration signal.
Claim 7
Independent Claim
186 words
A method of transferring data from a dynamic memory to a static memory, the static memory having a static memory cell with first and second nodes, the static memory cell having a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal, the method comprising the steps of: electrically isolating the static memory from the dynamic memory; equilibrating the electrically isolated static memory by activating a first equilibrate transistor connected between the first and second nodes, and activating a second equilibrate transistor connected between the drain of the grounding transistor and an equilibrate voltage; electrically coupling the static memory to the dynamic memory; imparting a differential voltage on the static memory; and storing the data in the static memory.
Claim 8
Independent Claim
186 words
A method of transferring data from a dynamic memory to a static memory, the static memory having a static memory cell with first and second nodes, the static memory cell having a first transistor having a gate connected to the second node, a drain connected to the first node, and a source connected to a drain of a grounding transistor, and a second transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the drain of the grounding transistor, the grounding transistor having a source coupled to ground potential, and a gate connected to receive an activation signal, the method comprising the steps of: electrically isolating the static memory from the dynamic memory; equilibrating the electrically isolated static memory by activating a first equilibrate transistor connected between the first and second nodes, and activating a second equilibrate transistor connected between the drain of the grounding transistor and an equilibrate voltage; electrically coupling the static memory to the dynamic memory; imparting a differential voltage on the static memory; and storing the data in the static memory.
Claim 9
Dependent Claim
30 words
The method of claim 4 wherein the step of electrically isolating the static memory comprises the step of: deactivating isolation transistors located between the static memory and the dynamic memory.
Claim 10
Dependent Claim
34 words
The method of claim 4 wherein the step of electrically coupling the static memory to the dynamic memory comprises the step of: activating isolation transistors located between the static memory and the dynamic memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |