US6184093B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of implementing differential gate oxide thickness for flash EEPROM
Assignee: Promos Technologies Inc
•
Filing: 1998-08-21
•
Granted: 2001-02-06
•
Expires: 2018-08-21
Abstract
Abstract Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer ( 120 ) that is thin in some regions, such as the cell region, and thicker in other regions ( 155 ), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.
Inventors
- 👤 Kuo-Tung Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:55
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/41; H10B41/42; H10B41/49; H10B69/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
162 words
A method of forming a semiconductor device comprising: providing a semiconductor substrate including a memory region and a periphery region; forming a first gate oxide layer having a first thickness on said semiconductor substrate; forming a first conducting layer on said first gate oxide layer; masking and patterning said first conducting layer and said first gate oxide layer to form a first memory gate electrode in said memory region and a first periphery gate electrode in said periphery region; forming by thermal oxidation a second gate oxide layer over a portion of said periphery region exclusive of said first periphery gate electrode, said second gate oxide layer having a second thickness different than said first thickness; forming a second conducting layer on at least said second gate oxide layer; masking and patterning said second conducting layer and said second gate oxide to form a second memory gate electrode in said memory region and a second periphery gate electrode in said periphery region.
Claim 2
Independent Claim
162 words
A method of forming a semiconductor device comprising: providing a semiconductor substrate including a memory region and a periphery region; forming a first gate oxide layer having a first thickness on said semiconductor substrate; forming a first conducting layer on said first gate oxide layer; masking and patterning said first conducting layer and said first gate oxide layer to form a first memory gate electrode in said memory region and a first periphery gate electrode in said periphery region; forming by thermal oxidation a second gate oxide layer over a portion of said periphery region exclusive of said first periphery gate electrode, said second gate oxide layer having a second thickness different than said first thickness; forming a second conducting layer on at least said second gate oxide layer; masking and patterning said second conducting layer and said second gate oxide to form a second memory gate electrode in said memory region and a second periphery gate electrode in said periphery region.
Claim 3
Dependent Claim
34 words
The method of claim 1 further comprising depositing and patterning a dielectric layer on said first memory gate electrode and on said first periphery gate electrode before said forming said second gate oxide layer.
Claim 4
Dependent Claim
24 words
The method of claim 2 wherein said dielectric layer is a oxide/nitride/oxide layer, and said first and second conducting layers are comprised of polysilicon.
Claim 5
Dependent Claim
15 words
The method of claim 2 wherein said dielectric layer is formed by chemical vapor deposition.
Claim 6
Dependent Claim
55 words
The method of claim 2 wherein said second memory gate electrode comprises a split gate cell control gate electrode over said portion of said first memory gate electrode and over a portion of said dielectric layer not over said first memory gate electrode, and where said first memory gate electrode comprises a floating gate electrode.
Claim 7
Dependent Claim
20 words
A semiconductor device formed by the method according to claim 5 wherein said semiconductor device comprises an EEPROM semiconductor device.
Claim 8
Dependent Claim
55 words
The method of claim 2 wherein said second memory gate electrode comprises a split gate cell floating gate electrode over said portion of said first memory gate electrode and over a portion of said dielectric layer not over said first memory gate electrode, and where said first memory gate electrode comprises a select gate electrode.
Claim 9
Dependent Claim
20 words
A semiconductor device formed by the method according to claim 7 wherein said semiconductor device comprises an EEPROM semiconductor device.
Claim 10
Dependent Claim
13 words
The method of claim 1 wherein said first thickness is about 30-150 Å.
Claim 11
Dependent Claim
22 words
The method of claim 9 wherein said first gate oxide layer is formed using a thermal oxidation process in an oxygen-containing furnace.
Claim 12
Dependent Claim
23 words
The method of claim 10 wherein said thermal oxidation process is at about 850° C. and about 760 torr for about 30 minutes.
Claim 13
Dependent Claim
13 words
The method of claim 9 wherein said second thickness is about 100-500 Å.
Claim 14
Dependent Claim
22 words
The method of claim 12 wherein said second gate oxide layer is formed using a thermal oxidation process in an oxygen-containing furnace.
Claim 15
Dependent Claim
23 words
The method of claim 13 wherein said thermal oxidation process is at about 850° C. and about 760 torr for about 30 minutes.
Claim 16
Dependent Claim
15 words
The method of claim 1 wherein said first thickness is about 70 Å or less.
Claim 17
Dependent Claim
21 words
The method of claim 4 wherein said second thickness for said second gate oxide layer is about 250 Å or less.
Claim 18
Dependent Claim
29 words
The method of claim 1 wherein said first thickness provides high driving capability for the semiconductor device, and said second thickness provides high voltage reliability of the semiconductor device.
Claim 19
Dependent Claim
14 words
The method of claim 1 wherein said semiconductor device comprises an EEPROM semiconductor device.
Claim 20
Dependent Claim
16 words
The method of claim 18 wherein said EEPROM semiconductor device comprises a flash EEPROM semiconductor device.
Claim 21
Dependent Claim
36 words
The method of claim 1 wherein said second memory gate electrode comprises a stack gate cell control gate electrode over said first memory gate electrode, and said first memory gate electrode comprises a floating gate electrode.
Claim 22
Dependent Claim
32 words
The method of claim 20 , wherein a third memory gate electrode is formed from said second conducting layer in said memory region, said third memory gate electode comprising a select gate.
Claim 23
Dependent Claim
20 words
A semiconductor device formed by the method according to claim 20 wherein said semiconductor device comprises an EEPROM semiconductor device.
Claim 24
Independent Claim
218 words
A method of fabricating an integrated circuit comprising a flash memory device, said method comprising: providing a substrate, said substrate having a flash memory cell region, an MOS device region, and a high voltage device region; forming a dielectric layer overlying said flash memory cell region and said MOS device region, said dielectric layer overlying said flash memory cell region being a tunneling layer, and said dielectric layer overlying said MOS device region being a gate dielectric region; forming a floating gate overlying a portion of said dielectric layer overlying said flash memory cell region and forming an MOS transistor gate overlying a portion of said dielectric layer overlying said MOS device region, said floating gate and said MOS transistor gate being defined from a first conductive layer; forming an interlayer dielectric overlying said floating gate and said MOS transistor gate; removing a portion of said interlayer dielectric overlying said MOS transistor gate and clearing said high voltage device region from oxides and nitrides; forming a thick dielectric layer overlying said high voltage device region; and forming a control gate overlying said floating gate and a high voltage gate overlying a portion of said thick dielectric layer overlying said high voltage device region, said control gate and said high voltage gate being derived from a second conductive layer.
Claim 25
Independent Claim
218 words
A method of fabricating an integrated circuit comprising a flash memory device, said method comprising: providing a substrate, said substrate having a flash memory cell region, an MOS device region, and a high voltage device region; forming a dielectric layer overlying said flash memory cell region and said MOS device region, said dielectric layer overlying said flash memory cell region being a tunneling layer, and said dielectric layer overlying said MOS device region being a gate dielectric region; forming a floating gate overlying a portion of said dielectric layer overlying said flash memory cell region and forming an MOS transistor gate overlying a portion of said dielectric layer overlying said MOS device region, said floating gate and said MOS transistor gate being defined from a first conductive layer; forming an interlayer dielectric overlying said floating gate and said MOS transistor gate; removing a portion of said interlayer dielectric overlying said MOS transistor gate and clearing said high voltage device region from oxides and nitrides; forming a thick dielectric layer overlying said high voltage device region; and forming a control gate overlying said floating gate and a high voltage gate overlying a portion of said thick dielectric layer overlying said high voltage device region, said control gate and said high voltage gate being derived from a second conductive layer.
References Cited (Backward Citations)
USRE35094E
Cited
US5066992A
Cited
US5202850A
Cited
US5278087A
Cited
US5493534A
Cited
US5440159A
Cited
US5680346A
Cited
US5445983A
Cited
US5432114A
Cited
US5658812A
Cited
US5606532A
Cited
US6004847A
Cited
US5587951A
Cited
US5888869A
Cited
US5953599A
Cited
US5960289A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |