US5440159A — Single layer polysilicon EEPROM having uniform th…

Claim 1

Independent Claim 308 words

An EEPROM transistor of the type having a single polysilicon layer comprising: an MOS transistor region, formed in a semiconductor substrate of a first conductivity type with a surface, having a generally linear subsurface active first stripe defined by a dopant of a second conductivity type, a second stripe of thin tunnel oxide adjoiningly traversing the first stripe, said second tunnel oxide having a thickness of at most 120 Å, a polysilicon third stripe having a portion traversing the first stripe parallel to and adjoining the second stripe, substantially all of the portion separated from the first stripe by essentially only the second stripe, with implanted ion source and drain regions disposed in the first stripe aligned on opposite lateral sides of the third stripe, the third stripe functioning as a gate electrode relative to the source and drain, a capacitor region formed in the semiconductor substrate adjacent to the transistor region having a subsurface active first plate of a parallel plate capacitor, defined by dopant of the second conductivity type, an insulative second plate of thin oxide over the first plate, said second plate of thin oxide having a thickness substantially equal to that of said second stripe, said second plate of thin oxide extending to and connecting with said second stripe of thin tunnel oxide to form a single thin oxide layer with substantially uniform thickness throughout and a third plate of polysilicon parallel to and disposed over the first and second plates and joining the third stripe distal to the portion, wherein the third stripe and the connected third plate are defined within a perimeter of the second stripe and connected second plate such that said third stripe and said connected third plate overlie only said thin oxide of said second stripe and connected second plate the third plate serving as a charge storage member.

Claim 2

Dependent Claim 308 words

An EEPROM transistor of the type having a single polysilicon layer comprising: an MOS transistor region, formed in a semiconductor substrate of a first conductivity type with a surface, having a generally linear subsurface active first stripe defined by a dopant of a second conductivity type, a second stripe of thin tunnel oxide adjoiningly traversing the first stripe, said second tunnel oxide having a thickness of at most 120 Å, a polysilicon third stripe having a portion traversing the first stripe parallel to and adjoining the second stripe, substantially all of the portion separated from the first stripe by essentially only the second stripe, with implanted ion source and drain regions disposed in the first stripe aligned on opposite lateral sides of the third stripe, the third stripe functioning as a gate electrode relative to the source and drain, a capacitor region formed in the semiconductor substrate adjacent to the transistor region having a subsurface active first plate of a parallel plate capacitor, defined by dopant of the second conductivity type, an insulative second plate of thin oxide over the first plate, said second plate of thin oxide having a thickness substantially equal to that of said second stripe, said second plate of thin oxide extending to and connecting with said second stripe of thin tunnel oxide to form a single thin oxide layer with substantially uniform thickness throughout and a third plate of polysilicon parallel to and disposed over the first and second plates and joining the third stripe distal to the portion, wherein the third stripe and the connected third plate are defined within a perimeter of the second stripe and connected second plate such that said third stripe and said connected third plate overlie only said thin oxide of said second stripe and connected second plate the third plate serving as a charge storage member.

Claim 3

Dependent Claim 12 words

The device of claim 1 wherein the first stripe comprises N-type material.

Claim 4

Dependent Claim 62 words

The device of claim 1 further comprising a second transistor sharing said subsurface active first stripe of said transistor region of the MOS transistor, one of the ion implanted source and drain regions serving as a first electrode of the second transistor and having a polysilicon stripe functioning as a gate electrode parallel to the third stripe of the MOS transistor region.

Claim 5

Dependent Claim 32 words

The device of claim 3 further comprising a second transistor ion implanted region on an opposite side of the polysilicon stripe from the one of the ion implanted source and drain regions.

Claim 6

Dependent Claim 18 words

The device of claim 4 further comprising a bit line contact contacting the second transistor ion implanted region.

Claim 7

Dependent Claim 34 words

The device of claim 5 further comprising a bias means contacting the subsurface active first stripe on an opposite side of the third stripe from the one of the implanted source and drain regions.

Claim 8

Dependent Claim 45 words

The device of claim 1 further comprising a third transistor having a subsurface source and drain electrodes and a gate electrode, one of said subsurface electrodes overlapping said subsurface active first plate whereby signals applied to said gate electrode can influence said charge storage member.

Claim 9

Dependent Claim 16 words

The device of claim 7 wherein said gate electrode is polysilicon coplanar with said third stripe.

Claim 10

Dependent Claim 261 words

An EEPROM transistor array of the type having a single polysilicon layer comprising, a semiconductor substrate of a first conductivity type with a surface having a plurality of generally parallel linear subsurface first stripes defined by a dopant of a second conductivity type, second stripes of thin tunnel oxide transverse to the first stripes and disposed on said surface, third stripes of polysilicon disposed parallel to and over the second stripes, separated from said first stripes by essentially only said second stripes, implanted ion source and drain regions disposed in the first stripes aligned on opposite lateral sides of the third stripes, the third stripes functioning as gate electrodes relative to the sources and drains, thereby forming a plurality of MOS transistors, a plurality of parallel plate capacitors, each adjacent to one of the MOS transistors and having a first plate with a subsurface active region defined by said dopant of the second conductivity type, an insulative second plate of thin oxide over the first plate, and a third plate of polysilicon parallel to and disposed over the first and second plates with extensions of the second and third plates joining said second and third stripes, respectively, each second plate and joined second stripe together forming a single thin oxide layer of substantially uniform thickness of at most 120 Å, the third plate serving as a charge storage member, wherein each transistor and associated capacitor has symmetry with other transistors and connected capacitors about both a first line substantially parallel with and a second line substantially perpendicular to said first stripes.

Claim 11

Dependent Claim 261 words

An EEPROM transistor array of the type having a single polysilicon layer comprising, a semiconductor substrate of a first conductivity type with a surface having a plurality of generally parallel linear subsurface first stripes defined by a dopant of a second conductivity type, second stripes of thin tunnel oxide transverse to the first stripes and disposed on said surface, third stripes of polysilicon disposed parallel to and over the second stripes, separated from said first stripes by essentially only said second stripes, implanted ion source and drain regions disposed in the first stripes aligned on opposite lateral sides of the third stripes, the third stripes functioning as gate electrodes relative to the sources and drains, thereby forming a plurality of MOS transistors, a plurality of parallel plate capacitors, each adjacent to one of the MOS transistors and having a first plate with a subsurface active region defined by said dopant of the second conductivity type, an insulative second plate of thin oxide over the first plate, and a third plate of polysilicon parallel to and disposed over the first and second plates with extensions of the second and third plates joining said second and third stripes, respectively, each second plate and joined second stripe together forming a single thin oxide layer of substantially uniform thickness of at most 120 Å, the third plate serving as a charge storage member, wherein each transistor and associated capacitor has symmetry with other transistors and connected capacitors about both a first line substantially parallel with and a second line substantially perpendicular to said first stripes.

Claim 12

Dependent Claim 24 words

The device of claim 9 further comprising a plurality of metal stripes generally parallel to the first stripes for electrical contact with the device,

Claim 13

Dependent Claim 24 words

The device of claim 9 further comprising a plurality of metal stripes generally parallel to the second stripes for electrical contact with the device,

Claim 14

Dependent Claim 32 words

The device of claim 9 further comprising a plurality of first metal stripes generally parallel to said first stripes and a plurality of second metal stripes generally parallel to said second stripes.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-08-07	1999-02-06	1999-08-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-08-07	2003-02-06	2003-08-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-08-07	2007-02-06	2007-08-08	$7700.00	Window Closed / Lapsed

Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer

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