US4823316A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Eeprom memory cell with a single polysilicon level and a tunnel oxide zone
Assignee: STMicroelectronics SRL
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Filing: 1987-11-12
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Granted: 1989-04-18
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Expires: 2007-11-12
Abstract
Abstract The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.
Inventors
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
93 words
EEPROM memory cell comprising a selection transistor, a pickup transistor with floating gate and control gate, and a tunnel condenser with thin oxide zone formed using a single layer of polysilicon for the floating gate and the tunnel condenser and at least one active area with n + diffusion for the control gate said thin oxide zone of the tunnel condenser being formed on an active area distinct and separate from that of the pickup transistor, the active area of the pickup transistor being serially connected with said diffusion of the control gate.
Claim 2
Dependent Claim
93 words
EEPROM memory cell comprising a selection transistor, a pickup transistor with floating gate and control gate, and a tunnel condenser with thin oxide zone formed using a single layer of polysilicon for the floating gate and the tunnel condenser and at least one active area with n + diffusion for the control gate said thin oxide zone of the tunnel condenser being formed on an active area distinct and separate from that of the pickup transistor, the active area of the pickup transistor being serially connected with said diffusion of the control gate.
Claim 3
Dependent Claim
88 words
Memory cell in accordance with claim 1 characterized in that said single polysilicon layer comprises a first part defining the gate of the selection transistor and a second part formed of a first arm superimposed on the thin oxide zone on said distinct and separate active area, a second arm superimposed on said at least one active area to form the floating gate of the pickup transistor and a space further superimposed on said at least one active area to form a coupling condenser of the control gate.
References Cited (Backward Citations)
US4754320A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |