US6004847A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
Assignee: STMicroelectronics SRL
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Filing: 1996-06-20
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Granted: 1999-12-21
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Expires: 2016-06-20
Abstract
Abstract A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.
Inventors
- 👤 Cesare Clementi
- 👤 Gabriella Ghidini
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:03
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
232 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented therein at least one matrix of non-volatile memory cells each having a floating gate and a control gate, each floating and control gate being electroconductive and electrically insulated from each other by means of an intermediate dielectric multilayer including a lower dielectric material layer and an upper silicon oxide layer, and the substrate also having simultaneous implementation in an area peripheral to the matrix of memory cells of at least a first transistor having a first gate dielectric of a first thickness, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer that forms the floating gate, and the lower dielectric material layer; (B) removal of the gate oxide layer, the polycrystalline layer, and the lower dielectric material layer from the area including the at least a first transistor; (C) deposition of the upper silicon oxide layer over the floating gate and over the substrate in the area including the at least first transistor; and (D) formation of a first silicon oxide layer in the area including the at least a first transistor, wherein step (D) comprises oxidation by high-temperature treatment of the substrate in the area including the first transistor in an oxidizing ambient allowing growth of the first silicon oxide layer between the upper silicon oxide layer and the substrate.
Claim 2
Dependent Claim
232 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented therein at least one matrix of non-volatile memory cells each having a floating gate and a control gate, each floating and control gate being electroconductive and electrically insulated from each other by means of an intermediate dielectric multilayer including a lower dielectric material layer and an upper silicon oxide layer, and the substrate also having simultaneous implementation in an area peripheral to the matrix of memory cells of at least a first transistor having a first gate dielectric of a first thickness, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer that forms the floating gate, and the lower dielectric material layer; (B) removal of the gate oxide layer, the polycrystalline layer, and the lower dielectric material layer from the area including the at least a first transistor; (C) deposition of the upper silicon oxide layer over the floating gate and over the substrate in the area including the at least first transistor; and (D) formation of a first silicon oxide layer in the area including the at least a first transistor, wherein step (D) comprises oxidation by high-temperature treatment of the substrate in the area including the first transistor in an oxidizing ambient allowing growth of the first silicon oxide layer between the upper silicon oxide layer and the substrate.
Claim 3
Dependent Claim
39 words
The process in accordance with claim 1, wherein the oxidizing ambient is at a temperature between 750° C. and 950° C. and in an atmosphere containing at least one of the following compounds: O 2 and H 2 O.
Claim 4
Dependent Claim
19 words
The process in accordance with claim 1, further comprising a step of high-temperature nitridizing said first silicon oxide layer.
Claim 5
Dependent Claim
251 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented therein at least one matrix of non-volatile memory cells each having a floating gate and a control gate, each floating and control gate being electroconductive and electrically insulated from each other by means of an intermediate dielectric multilayer including a lower dielectric material layer and an upper silicon oxide layer, and the substrate also having simultaneous implementation in an area peripheral to the matrix of memory cells of a first transistor having a first gate dielectric of a first thickness and a second transistor having a second gate dielectric of a second thickness, thinner than said first thickness, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer that forms the floating gate, and the lower dielectric material layer; (B) removal of the gate oxide layer, the polycrystalline layer, and the lower dielectric material layer from the area including the first and second transistors; (C) deposition of the upper silicon oxide layer over the floating gate and over the substrate in the area including the first and second transistors; (D) formation of a first silicon oxide layer in the area including the first and second transistors; (E) removal of the upper silicon oxide layer and said first silicon oxide layer from the area including said second transistor; and (F) formation of a second silicon oxide layer in both the area including the first transistor and the area including the second transistor.
Claim 6
Dependent Claim
251 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented therein at least one matrix of non-volatile memory cells each having a floating gate and a control gate, each floating and control gate being electroconductive and electrically insulated from each other by means of an intermediate dielectric multilayer including a lower dielectric material layer and an upper silicon oxide layer, and the substrate also having simultaneous implementation in an area peripheral to the matrix of memory cells of a first transistor having a first gate dielectric of a first thickness and a second transistor having a second gate dielectric of a second thickness, thinner than said first thickness, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer that forms the floating gate, and the lower dielectric material layer; (B) removal of the gate oxide layer, the polycrystalline layer, and the lower dielectric material layer from the area including the first and second transistors; (C) deposition of the upper silicon oxide layer over the floating gate and over the substrate in the area including the first and second transistors; (D) formation of a first silicon oxide layer in the area including the first and second transistors; (E) removal of the upper silicon oxide layer and said first silicon oxide layer from the area including said second transistor; and (F) formation of a second silicon oxide layer in both the area including the first transistor and the area including the second transistor.
Claim 7
Dependent Claim
22 words
The process in accordance with claim 4, wherein step (F) includes oxidation with a high-temperature treatment of the substrate in oxidizing ambient.
Claim 8
Dependent Claim
38 words
The process in accordance with claim 5, wherein the oxidizing ambient is at a temperature between 750° C. and 950° C. and an atmosphere containing at least one of the following compounds: O 2 and H 2 O.
Claim 9
Dependent Claim
19 words
The process in accordance with claim 4, further comprising the step of high-temperature nitridizing said second silicon oxide layer.
Claim 10
Dependent Claim
46 words
The process in accordance with claim 4, further comprising the step of partial surface removal of the upper silicon oxide layer from the area of the substrate including the first transistor and from the area of the substrate including the memory cells after performing step (E).
Claim 11
Dependent Claim
15 words
The process in accordance with claim 1, wherein the process is implemented in CMOS technology.
Claim 12
Dependent Claim
23 words
The process in accordance with claim 1, wherein a thickness of said upper silicon oxide layer is between 50 Å and 250 Å.
Claim 13
Dependent Claim
38 words
The process in accordance with claim 4, wherein a thickness of said upper silicon oxide layer is between 50 Å and 250 Å and said first thickness and said second thickness are between 70 Å and 350 Å.
Claim 14
Independent Claim
241 words
A method of fabricating an integrated circuit formed on a substrate, the integrated circuit including a memory cell, a first transistor and a second transistor, the memory cell including a floating gate, a control gate, and a multilayer dielectric for insulating the floating gate from the control gate, the first transistor including a first multilayer gate dielectric having a first thickness, and the second transistor including a second multilayer gate dielectric having a second thickness, the method comprising the steps of: (A) removal of the multilayer dielectric and the floating gate of the memory cell from an area on the substrate in which the first and second transistors are formed, the area being peripheral to an area in which the memory cell is formed; (B) depositing a first silicon oxide layer over the areas on the substrate in which the memory cell and the first and second transistors are formed; (C) forming a second silicon oxide layer in the area of the substrate in which the first and second transistors are formed; (D) removing the multilayer dielectric and the floating gate of the memory cell from an area on the substrate in which the second transistor is formed; (E) removing the first silicon oxide layer and the second silicon oxide layer from the area in which the second transistor is formed; and (F) forming a third silicon oxide layer in the areas in which the first and second transistors are formed.
Claim 15
Independent Claim
241 words
A method of fabricating an integrated circuit formed on a substrate, the integrated circuit including a memory cell, a first transistor and a second transistor, the memory cell including a floating gate, a control gate, and a multilayer dielectric for insulating the floating gate from the control gate, the first transistor including a first multilayer gate dielectric having a first thickness, and the second transistor including a second multilayer gate dielectric having a second thickness, the method comprising the steps of: (A) removal of the multilayer dielectric and the floating gate of the memory cell from an area on the substrate in which the first and second transistors are formed, the area being peripheral to an area in which the memory cell is formed; (B) depositing a first silicon oxide layer over the areas on the substrate in which the memory cell and the first and second transistors are formed; (C) forming a second silicon oxide layer in the area of the substrate in which the first and second transistors are formed; (D) removing the multilayer dielectric and the floating gate of the memory cell from an area on the substrate in which the second transistor is formed; (E) removing the first silicon oxide layer and the second silicon oxide layer from the area in which the second transistor is formed; and (F) forming a third silicon oxide layer in the areas in which the first and second transistors are formed.
Claim 16
Dependent Claim
15 words
The process of claim 12, wherein step (C) includes high temperature oxidation of the area.
Claim 17
Dependent Claim
41 words
The process of claim 12, wherein step (C) includes high temperature oxidation of the area in which the first transistor is formed and step (F) includes high temperature oxidation of the areas in which the first and second transistors are formed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |